PM5316

1.1 General
• Monolithic four channel SONET/SDH Payload Extractor/Aligner for use in STS-3 (STM- 1/AU-3) or STS-3c (STM-1/AU-4) interface applications, operating at serial interface speeds of 155.52 Mbit/s.
• Provides integrated clock recovery and clock synthesis for direct interfacing with optical modules.
• On each channel, provides termination for SONET section and line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of three STS-1 (STM- 0/AU-3) paths or a single STS-3c (STM-1/AU-4) path.
• On each channel, maps three STS-1 (STM-0/AU-3) payloads or a single STS-3c (STM- 1/AU-4) payload to the system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing.
• Provides Time Slot Interchange (TSI) function at the Telecom Add and Drop buses for grooming 12 STS-1 (STM-0/AU-3) paths.
• On each channel, provides clear-channel mapping of three 49.536 Mbit/s or 48.384 Mbit/s arbitrary data streams into an STS-3 (STM-1/AU-3) frame. Provides clear-channel mapping of a single 149.76 Mbit/s arbitrary data stream into an STS-3c (STM-1/AU-4) frame.
• Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from a Telecom Add bus interface to a Telecom Drop bus interface.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 3.3 V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3 V and 5 V compatible.
• Industrial temperature range (-40 °C to +85 °C).
• 520 pin Super BGA package.
• Complies with Telcordia GR-253-CORE (1995) jitter tolerance, jitter transfer and intrinsic jitter criteria.
1.2 SONET Section and Line/SDH Regenerator and Multiplexer Section
• Frames to the STS-3/3c (STM-1/AU-3/AU-4) receive stream and inserts the framing bytes (A1, A2) and the STS identification byte (J0) into the transmit stream; descrambles the receive stream and scrambles the transmit stream.
• Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for the receive stream and calculates and inserts B1 and B2 in the transmit stream; accumulates near end errors (B1, B2) and far end errors (M1) and inserts line remote error indications (REI) into the Z2 (M1) growth byte based on received B2 errors.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
• Extracts and serializes the order wire channels (E1, E2), the data communication channels (D1-D3, D4-D12) and the section user channel (F1) from the receive stream, and inserts the corresponding signals into the transmit stream.
• Extracts and serializes the automatic protection switch (APS) channel (K1, K2) bytes, filtering and extracting them into internal registers for the receive stream. Inserts the APS channel into the transmit stream.
• Extracts and filters the synchronization status message (Z1/S1) byte into an internal register for the receive stream. Inserts the synchronization status message (Z1/S1) byte into the transmit stream.
• Extracts a 64-byte or 16-byte section trace (J0) message using an internal register bank for the receive stream. Detects an unstable section trace message or mismatch with an expected message, and optionally inserts Line and Path AIS on the system Drop side upon either of these conditions. Inserts a 64-byte or 16-byte section trace (J0) message using an internal register bank for the transmit stream.
• Detects loss of signal (LOS), out-of-frame (OOF), loss-of-frame (LOF), line remote defect indication (RDI), line alarm indication signal (LAIS), and protection switching byte failure alarms on the receive stream. Optionally returns line RDI in the transmit stream.
• Provides a transmit and receive ring control port, allowing alarm and maintenance signal control and status to be passed between mate SPECTRA-155s for ring-based Add/Drop multiplexer and line multiplexer applications.
• Configurable to force Line AIS in the transmit stream.
1.3 SONET Path / SDH High Order Path
• Accepts a multiplex of three STS-1 (STM-0/AU-3) streams or a single STS-3c (STM-1/AU- 4) stream, interprets the STS (AU) pointer bytes (H1, H2, and H3), extracts the synchronous payload envelope(s) and processes the path overhead for the receive stream.
• Constructs a byte serial multiplex of three STS-1 (STM-0/AU-3) streams or an STS-3c (STM-1/AU-4) stream on the transmit side.
• Detects loss of pointer (LOP), loss of tributary multiframe (LOM), path alarm indication signal (PAIS) and path (auxiliary and enhanced) remote defect indication (RDI) for the receive stream. Optionally inserts PAIS, path RDI in the transmit stream.
• Extracts and serializes the entire path overhead from the three STS-1 (STM-0/AU-3) or the single STS-3c (STM-1/AU-4) receive streams. Inserts the path overhead bytes in the three STS-1 (STM-0/AU-3) or single STS-3c (STM-1/AU-4) stream for the transmit stream. The path overhead bytes may be sourced from internal registers or from bit serial path overhead input streams. Path overhead insertion may also be disabled.
• Extracts the received path signal label (C2) byte into an internal register and detects for path signal label unstable and for signal label mismatch with the expected signal label that is downloaded by the microprocessor. Inserts the path signal label (C2) byte from an internal register for the transmit stream.
• Extracts a 64-byte or 16-byte path trace (J1) message using an internal register bank for the receive stream. Detects an unstable path trace message or mismatch with an expected message, and inserts Path RAI upon either of these conditions. Inserts a 64-byte or 16-byte path trace (J1) message using an internal register bank for the transmit stream.
• Detects received path BIP-8 and counts received path BIP-8 errors for performance monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis. Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
• Counts received path REIs for performance monitoring purposes. Optionally inserts the path REI count into the path status byte (G1) basis on bit or block BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block bases independent of the accumulation of BIP-8 errors.
• Maintains the existing tributary multiframe sequence on the H4 byte until a new phase alignment has been verified.
• Provides a serial alarm port communication of path REI and path RDI alarms to the transmit stream of a mate SPECTRA-4x155 in the returning direction.
• Maintains the existing tributary multiframe sequence on the H4 byte until a new phase alignment has been verified.
1.4 System Side Interfaces
• Supports TelecomBus interfaces by indicating/accepting the location of the STS identification byte (C1), optionally the path trace byte(s) (J1), optionally the first tributary overhead byte(s) (V1), and all synchronous payload envelope (SPE) bytes in the byte serial stream.
• Configurable to support four 19.44 MHz byte TelecomBus interfaces or a single 77.76 MHz byte TelecomBus interface.
• For TelecomBus interface, accommodates phase and frequency differences between the receive/transmit streams and the Add/Drop buses via pointer adjustments.
• Provides TSI function to interchange or groom 12 STS-1 (STM-0/AU-3) paths or four STS- 3/3c (STM-1/AU-3/AU-4) paths at the Telecom Add/Drop buses.

The PM5316 SPECTRA 4X155 SONET/SDH Payload Extractor/Aligner terminates the transport and path overhead of four STS-3 (STM-1/AU-3) and STS-3c (STM-1/AU-4) streams at 155 Mbit/s. The device implements significant receive and transmit functions for a SONET/SDHcompliant line interface.

In the receive direction, the SPECTRA-4x155 receives SONET/SDH frames via bit serial interfaces, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path. The PM5316 performs framing (A1, A2), descrambling, alarm detection, and section and line bit interleaved parity (BIP) (B1, B2) monitoring, accumulating error counts at each level for performance monitoring purposes. The B2 errors are monitored to detect signal fail and degrade threshold crossing alarms. As part of this process, the PM5316 accumulates line REIs (M1) and may buffer and compare the 16 or 64-byte section trace (J0) message against the expected message.

The PM5316 also interprets the received payload pointers (H1, H2), detects path alarm conditions, and detects and accumulates path BIPs (B3). The path REIs are monitored and accumulated. Also, the 16 or 64-byte path trace (J1) message is accumulated and compared against the expected result. The PM5316 then extracts the SPE (VC). All transport and path overhead bytes are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired.

The extracted SPE (VC) PM5316 is placed on a Telecom Drop bus. Frequency offsets, for exampe, due to plesiochronous network boundaries, or the loss of a primary reference timing source, and phase differences, due to normal network operation, between the received data stream and the Drop bus are accommodated by pointer adjustments in the Drop bus.

In the transmit direction, the SPECTRA-4x155 transmits SONET/SDH frames, via bit serial interfaces, and formats section (regenerator section), line (multiplexer section), and path overhead appropriately. The PM5316 provides transmit path origination for a SONET/SDH STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) stream. PM5316 performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. Line REIs (M1) and a 16 or 64-byte section trace (J0) message may be optionally inserted. The PM5316 also generates the transmit payload pointers (H1, H2) and creates and inserts the path BIP. A 16 or 64-byte path trace (J1) message and the path status byte (G1) is optionally inserted.

In Addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-4x155 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-4x155 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors and BIP errors, which are useful for system diagnostics and tester applications.

The inserted SPE (VC) is sourced from a TelecomBus Add stream. The SPECTRA-4x155 maps the SPE (VC) from a Telecom Add bus into the transmit stream. As with the TelecomBus Drop stream, frequency offsets and phase differences between the transmit data stream and the Add bus are accommodated by pointer adjustments in the transmit stream.

The SPECTRA-4x155 supports Time-Slot Interchange (TSI) on the Telecom Add and Drop buses. On the Drop side, the TSI views the receive stream as 12 independent time-division multiplexed columns of data (12 constituent STS-1 (STM-0/AU-3) or equivalent streams or timeslots or columns). Any column can be connected to any time-slot on the Drop bus, independently of the channel they originate from. Both column swapping and broadcast are supported. TSI is independent of the underlying payload mapping formats. Similarly, on the Add side, data from the Add bus is treated as 12 independent time-division multiplexed columns. Assignment of data columns to transmit time-slots (STS-1 (STM-0/AU-3) or equivalent streams) is arbitrary.

The transmitter and receiver are independently configurable to allow for asymmetric interfaces. Ring control ports are provide to pass control and status information between mate transceivers. The SPECTRA-4x155 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.

The SPECTRA-4x155 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 520 pin SBGA package.