PM4328

`Integrates 28 T1 framers, 21 E1 framers and a full featured M13 multiplexer with DS3 framer in a single monolithic device for terminating DS3 multiplexed T1 or E1 streams.
`Four fundamental modes of operation:
`Up to 28 T1 streams M13 multiplexed into a serial DS3.
`Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data or H-MVIP system interfaces.
`DS3 M13 Multiplexer with ingress or egress per link monitoring.
`Unchannelized DS3 framer mode for access to the entire DS3 payload.
`Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial interface system-side devices. Also supports a fractional T1 or E1 system interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping.
`Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
`Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams or 3 DS3 streams.
`Provides jitter attenuation in the T1 or E1 receive and transmit directions.
`Provides two independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
`Provides per-DS0 line loopback and per link diagnostic and line loopbacks.
`Provides an on-board programmable binary sequence generator and detector for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151.
`Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152.
`Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
`Provides programmable idle code substitution, data and sign inversion, and digital milliwatt code insertion on a per-DS0 basis.
`Supports the M23 and C-bit parity DS3 formats.
`Standalone unchannelized DS3 framer mode for access to the entire DS3 payload.
`When configured to operate as a DS3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits.
`DS3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed).
`Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver and the PM8313 D3MX Multiplexer/Demultiplexer.
`Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
`Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
`Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
`324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40oC to 85oC) operation. Each one of 28 T1 receiver sections:
`Frames to DS-1 signals in SF and ESF formats.
`Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications.
`Accepts gapped data streams to support higher rate demultiplexing.
`Provides Red, Yellow, and AIS alarm integration.
`Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link.
`Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.
`Provides an HDLC interface with 128 bytes of buffering for terminating the facility data link.
`Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
`Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks.
`Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.
`A pseudo-random sequence user selectable from 211 1, 215 1 or220 1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1.
`Line side interface is the DS3 interface via the M13 multiplex.
`System side interface is either serial clock and data, H-MVIP or SBI bus.
`Frames in the presence of and detects the "Japanese Yellow" alarm.
`Provides external access for up to two de-jittered recovered T1 clocks. Each one of 21 E1 receiver sections:
`Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications.
`Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link.`Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233.
`V5.2 link indication signal detection.
`Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
`Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction.
`Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.
`Can be programmed to generate an interrupt on change of signaling state.
`Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.
`A pseudo-random sequence user selectable from 211 1, 215 1 or220 1, may be detected in the E1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire E1 or any combination of timeslots within the framed E1.
`Line side interface is the DS3 interface mutiplexed as per the G.747 recommendation.
`System side interface is either serial clock and data or H-MVIP.
`Provides external access for up to two de-jittered recovered E1 clocks. Each one of 28 T1 transmitter sections:
`May be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an N*8kHz reference.
`Provides minimum ones density through Bell (bit 7), GTE or "jammed bit 8" zero code suppression on a per-DS0 basis.
`Provides a 128 byte buffer to allow insertion of the facility data link using the host interface.
`Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in both SF and ESF formats.
`Provides a digital phase locked loop for generation of a low jitter transmit clock.
`Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
`Automatically generates and transmits DS-1 performance report messages to ANSI T1.231and ANSI T1.408 specifications.
`Supports the alternate ESF CRC-6 calculation for Japanese applications.
`A pseudo-random sequence user selectable from 211 1, 215 1 or 220 1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
`Line side interface is through the DS3 Interface via the M13 multiplex.
`System side interface is either serial clock and data, H-MVIP or SBI bus. Each one of 21 E1 transmitter sections:
`Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
`Transmits G.704 basic and CRC-4 multiframe formatted E1.
`Supports unframed mode and framing bit, CRC, or data link by-pass.
`Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis.
`Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.
`Provides a digital phase locked loop for generation of a low jitter transmit clock.
`A pseudo-random sequence user selectable from 2<sup>11</sup> 1, 2<sup>15</sup> 1 or 2<sup>20</sup> 1, may be inserted into the E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1.
`Optionally inserts a datalink in the E1 national use bits.
`Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233
`Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal.
`Line side interface is the DS3 interface mutiplexed as per the G.747 recommendation.
`System side interface is either serial clock and data or H-MVIP
DS3 Receiver Section:
`Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
`Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
`Provides indication of M-frame boundaries from which M-subframe boundaries and overhead bit positions in the DS3 stream can be determined by external processing.
`Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
`Extracts valid X-bits and indicates far end receive failure (FERF).
`Accumulates up to 65,535 line code violation (LCV) events per second, 65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.`Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
`Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled or interrupt-driven operation. Selectable none, one or two address match detection on first byte of received packet.
`Programmable pseudo-random test-sequence detection(up to 232 -1 bit length patterns conforming to ITU-T O.151 standards) and analysis features.
DS3 Transmit Section:
`Provides the overhead bit insertion for a DS3 stream.
`Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
`Provides B3ZS encoding.
`Generates an B3Zs encoded 100. repeating pattern to aid in pulse mask testing.
`Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by internal register bits.
`Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
`Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit paritapplication, C-bit parity error events, and far end block error (FEBE) events.
`Supports insertion of bit-oriented codes in the C-bit parity far end alarm and control channel.
`Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation.
`Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any repeating pattern up to 32 bits. The test pattern can be framed or unframed. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7.
M23 Multiplexer Section:
`Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
`Performs required bit stuffing/destuffing including generation and interpretation of C-bits.
`Includes required FIFO buffers for rate adaptation in the multiplex path.
`Allows insertion and detection of per DS2 payload loopback requests encoded in the C-bits to be activated under microprocessor control.
`Internally generates DS2 clock for use in integrated M13 or C-bit parity multiplex applications. Alternatively accepts external DS2 clock reference.
`Allows per DS2 alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control.
`Allows DS2 alarm indication signal (AIS) to be activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal.
`Supports C-bit parity DS3 format.
DS2 Framer Section:
`Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
`Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3 bit error rate.
`Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF).
`Accumulates up to 255 DS2 M-bit or F-bit error events per second.
DS2 Transmitter Section:
`Generates the required X, F, and M bits into the transmitted DS2 bit stream.  Allows inversion of inserted F or M bits for diagnostic purposes.
`Provides for transmission of far end receive failure (FERF) and alarm indication signal (AIS) under microprocessor control.
`Provides optional automatic insertion of far end receive failure (FERF) on detection of out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
M12 Multiplexer Section:
`Multiplexes four DS1 bit streams into a single M12 format DS2 bit stream.
`Performs required bit stuffing including generation and interpretation of Cbits.
`Includes required FIFO buffers for rate adaptation in the multiplex path.
`Performs required inversion of second and fourth multiplexed DS1 streams as required by ANSI T1.107 Section 7.2.
`Allows insertion and detection of per DS1 payload loopback requests encoded in the C-bits to be activated under microprocessor control.
`Allows per tributary alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control.
`Allows automatic tributary AIS to be activated upon DS2 out of frame.

The PM4328 High Density T1/E1 Framer with Integrated M13 Multiplexer (TECT3) is a feature-rich device for use in any applications requiring high density link termination over T1 or E1 channelized DS3.

The TECT3 supports asynchronous multiplexing and demultiplexing of 28 DS1s into a DS3 signal as specified by ANSI T1.107 and Bell Communications Research TR-TSY-000009.

This device can also be configured as a DS3 framer, providing external access to the full DS3 payload.

The TECT3 can be used as an M13 multiplexer with performance monitoring in either the ingress or egress direction for up to 28 T1s or 21 E1s. In this configuration the T1 and E1 transmit framers are disabled and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers for performance monitoring purposes.

Each of the T1 and E1 framers and transmitters is independently software configurable, allowing timing master and feature selection without changes to external wiring. This device is able to operate in T1 mode or E1 mode but not a mix of T1 and E1 modes.

In the ingress direction, each of the 28 T1 framers is demultiplexed from a channelized DS3 . Each T1 framer can be configured to frame to either of the common DS1 signal formats: (SF, ESF) or to be bypassed (unframed mode). Each T1 framer detects and indicates the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms.

T1 performance monitoring with accumulation of CRC-6 errors, framing bit rrors, out-of-frame events, and changes of frame alignment is provided. The ECT3 also detects the presence of ESF bit oriented codes, and detects and erminates HDLC messages on the ESF data link. The HDLC messages are erminated in a 128 byte FIFO. An elastic store that optionally supports slip uffering and adaptation to backplane timing is provided, as is a signaling xtractor that supports signaling debounce, signaling freezing and interrupt on ignaling state change on a per-DS0 basis. The TECT3 also supports idle code ubstitution, digital milliwatt code insertion, data extraction, trunk conditioning,  ata sign and magnitude inversion, and pattern generation or detection on a per- S0 basis.

In the egress direction, framing is generated for 28 T1s into the DS3. Each T1 ransmitter frames to SF or ESF DS1 formats, or framing can be optionally disabled. The TECT3 supports signaling insertion, idle code substitution, data nsertion, line loopback, data inversion and zero-code suppression on a per-DS0 asis. PRBS generation or detection is supported on a framed and unframed T1 asis.

In the ingress direction, each of the 21 E1 framers is extracted from the DS3 ollowing the ITU-T G.747 recommendation. Each E1 framer detects and ndicates the presence of remote alarm and AIS patterns and also integrates Red nd AIS alarms.

The E1 framers support detection of various alarm conditions such as loss of rame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers so support reception of mote alarm signal, remote multiframe alarm signal, larm indication signal, and time slot 16 alarm indication signal.

E1 performance monitoring with accumulation of CRC-4 errors, far end block rrors and framing bit errors is provided. The TECT3 provides a receive HDLC
controller for the detection and termination of messages on the national use bits.

Detection of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. V5.2 link ID signal detection is also supported. An interrupt may be generated on any change of state of the Sa codewords. An elastic store for slip buffering and rate adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided.

In the egress direction, framing is generated for 21 E1s into the DS3 following the ITU-T G.747 recommendation.Each E1 transmitter generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS generation or detection is supported on a framed and unframed E1 basis.

The TECT3 can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. Two low jitter recovered T1 clocks can be routed outside the TECT3 for network timing applications.

Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s ingress/egress system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.

In synchronous backplane systems 8Mb/s H-MVIP interfaces are provided for access to 672 DS0 channels, channel associated signaling (CAS) for all 672 DS0 channels and common channel signaling (CCS) for all 28 T1s. The DS0 data channel H-MVIP and CAS H-MVIP access is multiplexed with the serial PCM interface pins. The CCS signaling H-MVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1 slip buffers.

A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s both synchronously or asynchronously. The SBI allows transmit timing to be mastered by either the TECT3 or link layer device connected to the SBI bus. This interconnect allows up to 3 TECT3s to be connected in parallel to provide the full complement of 84 T1s of traffic. In addition to framed T1s, the TECT3 can transport unframed T1 links and framed or unframed DS3 links over the SBI bus.

When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TECT3 accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications.

In the DS3 receive direction, the TECT3 frames to DS3 signals with a maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, C-bit parity errors, far end block errors, AIS, far end receive failure and idle code. The DS3 framer is an off-line framer, indicating both out of frame (OOF) and change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still indicated while the framer is OOF, based on the previous frame alignment. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC channels are detected and are available through the microprocessor port. Error event accumulation is also provided by the TECT3. Framing bit errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, and far end block errors are accumulated. Error accumulation continues even while the off-line framers are indicating OOF. The counters are intended to be polled once per second, and are sized so as not to saturate at a 10-3 bit error rate. Transfer of count values to holding registers is initiated through the microprocessor interface.

In the DS3 transmit direction, the TECT3 inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals, Far End Receive Failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M sub-frame) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity application. Transmit timing is from an external reference or from the receive direction clock.

The TECT3 also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo Random Binary Sequence (PRBS) can be inserted into a DS3 payload and checked in the receive DS3 payload for bit errors. A fixed 100100. pattern is available for insertion directly into the B3ZS encoder for proper pulse mask shape verification.

When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of the DS3 signal. Bit stuffing and rate adaptation is performed. The C-bits are set appropriately, with the option of inserting DS2 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS3. AIS may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a stuffing ratio of 100%.

Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far end receive failure is detected and M-bit and F-bit errors are accumulated. The DS2 framer is an off-line framer, indicating both OOF and COFA events. Error events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated while the DS2 framer is indicating OOF, based on the previous alignment. Each of the seven 6312 kbit/s multiplexers may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s into and out of a DS2 formatted signal. Tributary frequency deviations are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 bloopback requests. Interrupts can be generated upon detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions.

When configured as a DS3 framer the unchannelized payload of the DS3 link is available to an external device.The TECT3 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.