PLXO

The Phase-locked Cyrstal Oscillator(PLXO) is a 16-pin, ceramic packaged devcie that provides frequency transition between telephone standard reference clocks associated with DS-1,DS-1C,and CEPT-1 transmission rates. Frequency tranistion of PLXO is accomplished using an internal, voltage-controlled crystal oscillator(VCXO) based phase-locked loop and user-supplied passive filter elements. The internal phase-locked loop provides two modes of operation. In locked mode, a low-pass filter with a large time constant (narrow bandwidth) is selected to provide a low noise output. In an out of lock mode, a low-pass filter with a comparing the relative edges of 8 kHz clocks supplied by the input clock and the internal VCXO, the phase detector determines if the loop is in or out oflock. Once lock is achieved, the phase detector switches from wide bandwidth filtering to narrow bandwidth filtering . To achieve PLXO, the two outputs of the phase detector(FSTFLT and SLWFLT) are altermately set to a high-impedance state and drive a lead-lag filter created using user-supplied elements. The PLXO will fully track the long-term stability of an inbound clock to ±130 ppm of the nominal value over its full power supply and temperature range(-40 to +85). At 25, with VDD equal to 5 V, and no inbound clock present, the free-fun frequency of the VCXO(at CLKOUT) will fall within ±75 ppm of the nominal value. The CLKOUT frequency will fall within ±130 ppm of the nominal value over the VCXO's full voltage and temperature range.

There are some general specifications about PLXO.Supply voltage(V_DD) is 4.5 V min and 5.5 V max. SUpply current(I_DD) is 5 mA min and 30 mA max when V_DD is 5.50 V. Input voltage levels: Input logic high(V_IH) is 2.0 V min and Input logic low(V_IL) is 0.8 V. Output voltage levels: Output logic high(V_OH) is 2.5 V min and Output logic low(V_IL) is 0.5 V max.Transition times: rise time(t_rise) is 0.5 ns min and 5.0 ns max while fall time(T_fall) is 0.5 ns min and 5.0 ns max. SYmmetry or duty cycle(options 1 and 2) : Output clock(CLKOUT) is 45% min and 55% while Output VCXO clock(V_COCLK) is 45% min and 55% max. 

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