PLUS405-55

NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two  complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1).

All state transition terms of PLUS405-55 can include True, False and Don't Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms of PLUS405-55 can be connected to any or all of the State and Output Registers.

All state (QP0 - QP7) and output (QF0 - QF7) registers PLUS405-55 are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level "1".

PLUS405-55 feature allows the state machine to be asynchronously initialized to known internal state and output conditions prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to "1". If desired, the initialization input pin (INIT)of PLUS405-55 can be converted to an Output Enable (OE) function as an additional user-programmable feature.

Availability of two user-programmable clocks of PLUS405-55 allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. Order codes are listed in the Ordering Information Table below.