Features: • PLUS405-37 fMAX = 37MHz 50MHz clock rate• PLUS405-45 fMAX = 45MHz 58.8MHz clock rate• Functional superset of PLS105/105A• Field-programmable (Ti-W fusible link)• 16 input variables• 8 output functions• 64 transition terms• 8-bit State...
PLUS405-37: Features: • PLUS405-37 fMAX = 37MHz 50MHz clock rate• PLUS405-45 fMAX = 45MHz 58.8MHz clock rate• Functional superset of PLS105/105A• Field-programmable (Ti-W fusible lin...
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Features: ·International standard packages JEDEC TO-264 and PLUS247TM·Low switching losses, low V(...
Features: SpecificationsDescriptionThe PLUS105-70 is a bipolar programmable state machine of the M...
SYMBOL |
PARAMETER |
RATING |
UNIT |
VCC |
Supply voltage |
+7 |
VDC |
VIN |
Input voltage |
+5.5 |
VDC |
VOUT |
Output voltage |
+5.5 |
VDC |
IIN |
Input currents |
-30to+30 |
mA |
IOUT |
Output currents |
+100 |
mA |
TAMB |
Operating free-air temperature range |
0 to+75 |
|
TSTG |
Storage temperature range |
-65 to +150 |
The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1).
All state transition terms PLUS405 can include True, False and Don't Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR PLUS405 array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers.
All state (QP0 - QP7) and output (QF0 - QF7) registers PLUS405 are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level "1". This feature allows the state machine to be asynchronously initialized to known internal state and output conditions, prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to "1". If desired, the initialization input pin (INIT)of PLUS405 can be converted to an Output Enable (OE) function as an additional user-programmable feature.
Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each.
Order codes are listed in the Ordering Information Table.