Features: • Selectable 750kHz to 800MHz range.• Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz).• 12 to 25MHz crystal input.• No external load capacitor or varicap required.• Inverted LVDS ...
PLL502-39U: Features: • Selectable 750kHz to 800MHz range.• Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz).• 12 ...
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PARAMETERS |
SYMBOL |
MIN. |
MAX. |
UNITS |
Supply Voltage |
VDD |
4.6 |
V | |
Input Voltage, dc |
VI |
-0.5 |
VDD+0.5 |
V |
Output Voltage, dc |
VO |
-0.5 |
VDD+0.5 |
V |
Storage Temperature |
TS |
-65 |
150 |
|
Ambient Operating Temperature* |
TA |
-40 |
85 |
|
Junction Temperature |
TJ |
125 |
||
Lead Temperature (soldering, 10s) |
260 |
|||
ESD Protection, Human Body Model |
2 |
kV |
The PLL502-39U (LVDS) is a high performance and low phase noise VCXO clock IC. It provides phase noise performance as low as 125dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The wide pull range (+/- 200 ppm) and very low jitter makes PLL502-39U for a wide range of applications, including SONET/SDH and FEC. PLL502-39 accepts fundamental parallel resonant mode crystals input from 12 to 25MHz.