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PLL130-68

Features: • Differential PECL (PLL130-68) or LVDS (PLL130-69) output.• Accepts any single-ended REFIN input (with as low as 100mV swing).• Internal AC coupling of REFIN• Input range from 1.0MHz to 1.0 GHz.• No Vref required.• No external current source required....

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SeekIC No. : 004463308 Detail

PLL130-68: Features: • Differential PECL (PLL130-68) or LVDS (PLL130-69) output.• Accepts any single-ended REFIN input (with as low as 100mV swing).• Internal AC coupling of REFIN• Inpu...

PLL130-68 Data Sheet

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Part Number:
PLL130-68
Supply Ability:
5000

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Product Details

Description



Features:

• Differential PECL (PLL130-68) or LVDS
  (PLL130-69) output.
• Accepts any single-ended REFIN input (with
  as low as 100mV swing).
• Internal AC coupling of REFIN
• Input range from 1.0MHz to 1.0 GHz.
• No Vref required.
• No external current source required.
• 2.5 to 3.3V operation.
• Available in 3x3mm QFN.


Pinout

Connection Diagram


Specifications

PARAMETERS SYMBOL MIN. MAX. UNITS
Supply Voltage VDD   4.6 V
Input Voltage, dc VI -0.5 VDD+0.5 V
Output Voltage, dc VO -0.5 VDD+0.5 V
Storage Temperature TS -65 150 °C
Ambient Operating Temperature TA -40 85 °C
Junction Temperature TJ   125 °C
Lead Temperature (soldering, 10s)     260 °C
ESD Protection, Human Body Model     2 kV
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.


Description

The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential outputs (PECL for PLL130-68 or LVDS for PLL130- 69). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or PECL.




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