Features: ` 3.3V version of PI49FCT805/806` Extremely low output skew: 0.5ns` Monitor ouput pin` Clock busing wih 3-state control` TTL inpu and CMOS output compatible` Industrial operation at40°C to 85°C` Extremely low static power (1mW, typ.)` Hysteresis on all inputs` Packages available:20-pin 3...
PI49FCT3806A: Features: ` 3.3V version of PI49FCT805/806` Extremely low output skew: 0.5ns` Monitor ouput pin` Clock busing wih 3-state control` TTL inpu and CMOS output compatible` Industrial operation at40°C to...
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Features: • High Frequency >150 MHz• High-speed, low-noise, non-inverting clock buf...
Above which the useful life may be impaired. For user guidelines, not tested.
Storage Temperature ............................................................ 65°C to +150°C
Ambient Temperature with Power Applied .............................. 40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & I/O Only) ....... 0.5V to +7.0V
DC Input Voltage ....................................................................... 0.5V to +7.0V
DC Output Current ................................................................................ 120 mA
Power Dissipation .................................................................................... 0.5W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Pericom Semiconductor's PI49FCT series of logic circuits are produced using the Company's advanced submicron CMOS technology, achieving industry leading speed grades.
In the PI49FCT series , the PI49FCT3805 is a 3.3V non-inverting clock driver and the PI49FCT3806 is a 3.3V inverting clock driver designed with two independent groups of buffers. These buffers have 3-state Output Enable inputs (active LOW) with a 1-in, 5-out configuration per group. Each clock driver consist of two banks of drivers, driving five outputs each from a standard TTL compatible CMOS input.