PFLDL-TTL-5-5

The PFLDL-TTL PFLDL-TTL-5-5 is offered in 23 models with time delays to a maximum of 355ns and with step resolution.A complmentary(OUT)output is provided approximately 1ns after normal output.PFLDL-TTL-5-5 can be driven by a standard Schottky T2L gate. Output is FSAT T2L toggle;programming inputs are FAST T2L single fan-in.These logic delay lines have the capability of driving up to 10 T2L loads.These"DIP Series" programmable logic delay lines are packaged in a 14-pin DIP housing, molded of flameproof Dially Phthalate per MIL-M-14, type SDG-F, and are fully encapsulated in epoxy resin.Thru-hole,J,Gull wing or Turked lead configurations are available on these modules. Leads meet the solderability requirements of MIL-STD-202, Method 208.PFLDL-TTL-5-5 has many unique features: the first one is delays stable and precise. The second one is 14-pin DIP package. The third one is it is available in delays up to 355 nS. The forth one is propagation delays fully compenstated. The fifth one is all delays are digitally programmable,etc. 

There are some operating specifications of PFLDL-TTL-5-5.Supply voltage is 4.75 V DC to 5.25 V DC. Supply current is 40 mA typical. Logic 0 input: Voltage is 2 V min and 5.5 V max . Current is 40 uA max when it is at 2.7 V and is 2 mA max when It is at 5.5 V.Logic 1 voltage out is 2.7 V min. Logic 0 voltage out is .5 V max. Operating temperature range is 0 to 70. Storage temperature is -55 to +125.

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