Features: Ultra Low Power Operation- Vcc = 5 Volts ±10%- Icc = 10 µA (typical) at standby- Icc = 2 mA (typical) at 1 MHzCMOS Electrically Erasable Technology- Superior factory testing- Reprogrammable in plastic package- Reduces retrofit and development costsApplication Versatility- Replaces ...
PEEL18CV8Z: Features: Ultra Low Power Operation- Vcc = 5 Volts ±10%- Icc = 10 µA (typical) at standby- Icc = 2 mA (typical) at 1 MHzCMOS Electrically Erasable Technology- Superior factory testing- Reprogr...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: · Ultra Low Power Operation- VCC = 5 Volts ±10%- Icc = 10 µA (typical) at standby-...
Features: High Speed/Low Power- Speeds ranging from 7ns to 25ns- Power as low as 30mA at 25MHzElec...
Symbol |
Parameter |
Conditions |
Rating |
Unit |
VCC VO IO TST TLT |
Supply Voltage Voltage Applied to Any Pin2 Output Current Storage Temperature Lead Temperature |
Relative to Ground Relative to Ground1 Per Pin (IOL, IOH) Soldering 10 Seconds |
-0.5 to +6.0 -0.5 to VCC +0.6 +25 -65 to +150 +300 |
V V mA |
The PEEL™18CV8Z is a Programmable Electrically Erasable Logic (PEEL™) SPLD (Simple Programmable Logic Device) that features ultra-low, automatic "zero" power-down operation. The "zero power" (100 µA max. Icc) power-down mode makes the PEEL™18CV8Z ideal for a broad range of battery-powered portable equipment applications, from hand-held meters to PCM- CIA modems. EE-reprogrammability provides both the conve- nience of fast reprogramming for product development and quick product personalization in manufacturing, including Engineering Change Orders.
The PEEL™18CV8Z is logically and functionally similar to Anachip's 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z. The differences between the PEEL™18CV8Z and PEEL™18CV8 include the addition of programmable clock polarity, a product term clock, and variable width product terms in the AND/OR Logic Array.
Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z provides additional architectural features that allow more logic to be incorporated into the design. Anachip's JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEEL™18CV8Z architecture without the need for redesign. The PEEL™18CV8Z architecture allows it to replace over twenty standard 20-pin DIP, SOIC, TSSOP and PLCC packages.