PEEL18CV8P-10

Number of Macrocells : 8
Number of Programmable I/Os : 8
Operating Supply Voltage : 5 V
Delay Time : 10 ns
Supply Current : 90 mA
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Package / Case : PDIP-20
Logic Family : PEEL
Maximum Operating Frequency : 100 MHz


Pinout




Description

The PEEL18CV8P-10 is one member of the PEEL18CV8 series.The PEEL18CV8 is a programmable electrically erasable logic (PEEL) device providing an attractive alternative to ordinary PLDs.The PEEL18CV8 offers the performance,flexibility, ease of design and production practicality needed by logic designers today.

Features of the PEEL18CV8 are:(1)multiple speed power, temperature options;(2)CMOS electrically erasable technology;(3)reduces retrofit and development costs;(4)commercial and industrial versions available.The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP packages with speeds ranging from 5ns to 25ns with power consumption as low as 37mA. EE-Reprogrammability provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of programming changes or errors.

The absolute maximum ratings of the PEEL18CV8 can be summarized as:(1)supply voltage Vcc:-0.5 to + 6.0 V;(2)output current Io:±25mA;(3)storage temperature Tst:-65 to +150 °C;(4)lead temperature Tlt:+300 °C.This device has been designed and tested for the specified operating ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.Parameters are not 100% tested.Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency.Feedback also can be taken from the register, regardless of whether the output function is to be combinatorial or registered. When implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output.

The PEEL18CV8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the PEEL18CV8P-10 has been programmed. Once the security bit is set it is impossible to verify (read) or program the PEEL until the entire device has first been erased with the bulk-erase function.