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PEB20590

Features: VIP is a universal ISDN transceiver IC for differentinterface modes (S/T or UPN).• Eight 2B+D line interfaces with full duplex transceivers S/T interfaces at 192 kbit/s with line transceivers according to ITU-T I.430, ETSI 300.012 and ANSI T1.605 UPN interfaces at 384 kbit/s with l...

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PEB20590: Features: VIP is a universal ISDN transceiver IC for differentinterface modes (S/T or UPN).• Eight 2B+D line interfaces with full duplex transceivers S/T interfaces at 192 kbit/s with line tra...

PEB20590 Data Sheet

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Part Number:
PEB20590
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

VIP is a universal ISDN transceiver IC for differentinterface modes (S/T or UPN).
• Eight 2B+D line interfaces with full duplex transceivers
S/T interfaces at 192 kbit/s with line transceivers according to ITU-T I.430, ETSI 300.012 and ANSI T1.605
UPN interfaces at 384 kbit/s with line transceivers according to ZVEI standard
Receive timing recovery
Conversion between pseudo-ternary and binary codes
Conversion between UPN or S/T frames and IOM-2000 frame structures
Execution of test loops
Frame alignment in trunk applications with maximum wander correction of ± 25 µs
UPN interface compatible to OCTAT-P (PEB 2096)1)
S/T interface compatible to QUAT-S (PEB 2084)2)
• IOM-2000 interface to DELIC supporting up to three VIPs (24 channels)
Transceiver initialization and configuration
Control of layer-1 activation/deactivation
Exchange of command and status information
• Signaling control for all VIP channels by dedicated HDLC controllers in DELIC
• Single 3.3 V power supply
• JTAG IEEE1149.1-compliant test interface with dedicated reset input
Note: UPN refers to a version of the UP0 interface (meeting the ZVEI standard) with a
reduced loop length of up to 1.3 km, depending on the type of cable.


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Limit Values
Unit
Storage temperature
Tstg
65 to 150
°C
IC supply voltage
VDD
0.3 to 4.6
V
DC input voltage (except I/Os)
VI
0.3 to 6.0
V
DC output voltage (including I/Os);
output in high or low state
VO
0.3 to VDD + 0.3
V
DC output voltage (including I/Os);
output in tri-state
VI, VO
0.3 to 6.0
V
ESD robustness 1)
HBM: 1.5 kΩ, 100 pF
VESD,HBM
2000
V
1) According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. The SX pins are not
protected against voltage stress > 1500 V (versus VS or GND).
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.



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