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PEB20525

Features: Serial communication controllers (SCCs)• Two independent channels• Full duplex data rates on each channel of up to12.5 Mbit/s sync - 2 Mbit/s with DPLL• 64 Bytes deep receive FIFO per SCC• 64 Bytes deep transmit FIFO per SCCSerial Interface• On-chip clock ge...

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PEB20525: Features: Serial communication controllers (SCCs)• Two independent channels• Full duplex data rates on each channel of up to12.5 Mbit/s sync - 2 Mbit/s with DPLL• 64 Bytes deep rec...

PEB20525 Data Sheet

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Part Number:
PEB20525
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

Serial communication controllers (SCCs)
• Two independent channels
• Full duplex data rates on each channel of up to
12.5 Mbit/s sync - 2 Mbit/s with DPLL
• 64 Bytes deep receive FIFO per SCC
• 64 Bytes deep transmit FIFO per SCC
Serial Interface
• On-chip clock generation or external clock sources
• On-chip DPLLs for clock recovery
• Baud rate generator
• Clock gating signals
• Clock gapping capability
• Programmable time-slot capability for connection to
TDM interfaces (e.g. T1, E1)
• NRZ, NRZI, FM and Manchester data encoding
• Optional data flow control using modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision detection and resolution
Bit Processor Functions
• HDLC/SDLC Protocol Modes
Automatic flag detection and transmission
Shared opening and closing flag
Generation of interframe-time fill '1's or flags
Detection of receive line status
Zero bit insertion and deletion
CRC generation and checking (CRC-CCITT or CRC-32)
Transparent CRC option per channel and/or per frame
Programmable Preamble (8 bit) with selectable repetition rate
Error detection (abort, long frame, CRC error, short frames)
• Bit Synchronous PPP Mode
Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
Zero bit insertion/deletion
15 consecutive '1' bits abort sequence
• Octet Synchronous PPP Mode
Octet oriented transmission of HDLC frame (flag, data, CRC, flag)
Programmable character map of 32 hard-wired characters (00H-1FH)
Four programmable characters for additional mapping
Insertion/deletion of control-escape character (7DH) for mapped characters
• Extended Transparent Mode
Fully bit transparent (no framing, no bit manipulation)
Octet-aligned transmission and reception
• Protocol and Mode Independent
Data bit inversion
Data overflow and underrun detection
Timer
Protocol Support
• Address Recognition Modes
No address recognition (Address Mode 0)
8-bit (high byte) address recognition (Address Mode 1)
8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode
• HDLC Automode
8-bit or 16-bit address generation/recognition
Support of LAPB/LAPD
Automatic handling of S- and I-frames
Automatic processing of control byte(s)
Modulo-8 or modulo-128 operation
Programmable time-out and retry conditions
SDLC Normal Response Mode (NRM) operation for slave
• Signaling System #7 (SS7) support
Detection of FISUs, MSUs and LSSUs
Unchanged Fill-In Signaling Units (FISUs) not forwarded
Automatic generation of FISUs in transmit direction (incl. sequence number)
Counting of errored signaling units
• Optional DTACK/READY controlled cycles
Microprocessor Interface
• 8-bit bus interface (P-LFBGA-80-2 package)
• 8/16-bit bus interface (P-TQFP-100-3 package)
• Multiplexed and De-multiplexed address/data bus
• Intel/Motorola style
• Asynchronous interface
• Maskable interrupts for each channel
General Purpose Port (GPP) Pins (up to 3 in P-LFBGA-80-2, up to 7 in P-TQFP-100-
3 package)
General
• 3.3V power supply with 5V tolerant inputs
• Low power consumption
• Power safe features
• P-TQFP-100-3 Package (Thermal Resistance: RJA = 42 K/W)
• Small P-LFBGA-80-2 Package (Thermal Resistance: RJA = 51 K/W)


Pinout

Connection Diagram


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