PEB2046

The MTSS PEB 2046 is a monolithic CMOS device which has the ability to connect any of the 256 PCM channels of eight incoming PCM lines to any of the 256 PCM channels of eight output lines.

The input information of a complete frame PEB 2046 is stored in the speech memory SM. The incoming 256 channels of 8 bits each are written in sequence into fixed positions in the SM. PEB 2046 is controlled by the input counter in the timing control block with an 8-kHz repetition rate.

For output, the connection memory (CM) is read in sequence.Each location of PEB 2046 in CM points to a location in the speech memory. The byte in this speech memory location is read into the current output time-slot. The read access of the CM PEB 2046 is controlled by the output counter which also resides in the timing control block.

Thus the CM PEB 2046 needs to be programmed beforehand for the desired connection. The CM PEB 2046 address corresponds to one particular output time-slot and line number. The contents of this CM-address point to a particular input time-slot and line number (now resident in the SM).