PEB2045

The MTSC PEB 2045 is a monolithic CMOS circuit, which has the ability to connect any of the 512 PCM channels of 16 incoming PCM lines to any of the 256 PCM channels of eight output lines.

The PCM information for a complete frame is stored in the 4-Kbit speech memory SM, i.e. all of the 512 words with 8 bits are written into a fixed position of the SM. This is controlled by the input counter every 125 ms. The words of PEB 2045 are read using random access with an address that is stored in a connection memory CM for each of the 256 output channels. The access to the CM is controlled by the output counter.

To produce a connection the SM  PEB 2045 address and the CM address must be written into the PEB 2045 via a mP interface. The SM-address contains the time-slots and line numbers of the incoming PCM words. The CM address consists of the time-slots and line numbers of the output words.

The PEB 2045 can be connected to 2-Mbit/s, 4-Mbit/s and 8-Mbit/s PCM systems, the device clock may be either 4.096 MHz or 8.192 MHz.

In a second operational mode the PEB 2045 together with the PEB 2035 (ACFA, Advanced CMOS Frame Aligner) and the PEB 2235 (IPAT, ISDN Primary Access Transceiver) implements the system interface of up to four primary multiplex access lines. This interface of PEB 2045 can be configured for 2-Mbit/s, 4-Mbit/s and 8-Mbit/s systems; a clock shift for input and output lines with half clock step resolution is programmable. Selection of operating modes and rogramming is made by writing to the mode register and, via the Indirect Access Register (IAR), the Clock Shift Register (CSR) and the General Configuration Register (GCR).

The components PEB 2045 and PEF 2045 are functionally identical. The difference between the two types lies in the temperature range. The PEB 2045 operates in the temperature range 0 to 70 , the PEF 2045 in the range 40 to 85 .