PDSP16488A

·  The PDSP16488A is a replacement for the PDSP16488 (see Note below)
·  8 or 16-bit Pixels with rates up to 40 MHz
·  Window Sizes up to 838 with a Single Device
·  Eight Internal Line Delays
·  Supports Interlace and Frame-to-Frame Operations
·  Coefficients Supplied from an EPROM or Remote Host
·  Expandable in both X and Y for Larger Windows
·  Gain Control and Pixel Output Manipulation
·  84-pin PGA or 132-pin QFP Package Options
Note: PDSP16488A devices are not guaranteed to cascade with PDSP16488 devices. Mitel Semiconductor do not recommend that PDSP16488A be mixed with PDSP16488 devices in a single equipment design. The PDSP16488A requires external pullup resistors in EPROM Mode (see  Static Electrical Characteristics).

Supply voltage, V_DD......................-0`5V to 17`0V
Input voltage, V_IN.................... -0`5V to V<sub>DD</sub> 10`5V
Output voltage, V_OUT ..................-0`5V to V<sub>DD</sub> 10`5V
Clamp diode current per pin, I_K (see note 2) .............18mA
Static discharge voltage (HBM) ......................500V
Storage temperature, T_S ..................-65 to1150
Maximum junction temperature, T_JMAX
Commercial grade .............................+95
Industrial grade ..............................+110
Military grade ................................+150
ackage power dissipation ........................2000mW
Thermal resistance, junction-to-case, _JC ................5/W
NOTES
1.Exceeding these ratings may cause permanent damage.
   Functional operation under these conditions is not implied.
2.Maximum dissipation should not be exceeded for more than1 second, only one output to be tested at any one time.
3.Exposure to absolute maximum ratings for extended periods may affect device reliablity.
4.Current is defined as negative into the device.

The PDSP16488A is a fully integrated, application specific, image processing device. It  performs a two dimensional convo-lution between the pixels within a video window and a set of stored coefficients. An internal multiplier accumulator array can be multi-cycled at double or quadruple the pixel clock rate. This then gives the window size options listed in Table 1.

An internal 32kbit RAM can be configured to provide either four or eight line delays. The length of each delay can be programmed to the users requirement, up to a maximum of 1024 pixels per line. The line delays of PDSP16488A are arranged in two groups,which may be internally connected in series or may  be configured to accept separate pixel inputs. This allows interlaced video or frame to frame operations to be supported.

The 8-bit coefficients are also stored internally and can be downloaded from a host computer or from an EPROM. No additional logic is required to support the EPROM and a single PDSP16488A can support up to 16 convolvers.

The PDSP16488A contains an expansion adder and delay network which allows several devices to be cascaded. Con-volvers with larger windows can then be fabricated as shown in Table 2.

Intermediate 32-bit precision is provided by PDSP16488A to avoid any danger of overflow, but  the final result will not normally occupy all bits.

The PDSP16488A thus provides a gain control block in the output path, which allows the user to align the result to the most significant end of the 32-bit word.