PDSP16256

·  Sixteen MACs in a Single Device v Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates
·  Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3·125MHz
·  16-bit Data and 32-bit Accumulators
·  Can be configured as One Long Filter or Two Half-Length Filters
·  Decimate-by-two Option will Double the Filter Length
·  Coefficients supplied from Host System or local EPROM

·  High Performance Digital Filters

Supply voltage, V_DD                                    -0 5V to +7 0V
Input voltage, V_IN                               -0 5V to V_DD +0 5V
Output voltage, V_OUT                          -0 5V to V_DD +0 5V
Clamp diode current per pin, IK (see note 2)            18mA
Static discharge voltage (HBM)                                  500V
Storage temperature, T_S                            -65 to+150
Maximum junction temperature, T_JMAX
Commercial grade                                                   +100
Industrial grade                                                      +110
Military grade                                                          +150
Package power dissipation                                 3000mW
Thermal resistance, Junction-to-Case, _JC             5°C/W
NOTES
1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions
is not implied.
2. Maximum dissipation should not be exceeded for more than 1 second, only one output to be tested at
any one time.
3. Exposure to absolute maximum ratings for extended periods may affect device reliablity.
4. Current is defined as negative into the device.
5. The JC data assumes that heat is extracted from the top of the package.
6. Maximum junction temperature, TJMAX, is specified with power applied.

The PDSP16256 contains sixteen multiplier -accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two's complement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits.

In 16-tap mode the device samples data at the system clock rate of up to 25MHz. If a lower sample rate is acceptable then the PDSP16256 can be increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the sample clock rate of PDSP16256 must be halved with respect to the system clock. With 128 stages the sample clock is therefore one eighth of the system clock.

In all speed modes PDSP16256 can be cascaded to provide filters of any length, only limited by the possibility of accumulator overflow. The 32-bit results are passed between cascaded devices without any intermediate scaling and subsequent loss of precision.

The PDSP16256 can be configured as either one long filter or two separate filters with half the number of taps in each. Both networks can have independent inputs and outputs.

Both single and cascaded devices can be operated in decimate-by-two mode. The output rate of PDSP16256 is then half the input rate, but twice the number of stages are possible at a given sample rate. A single device with a 20MHz clock would then, for example, provide a 128-stage low pass filter, with a 5MHz input rate and 2`5MHz output rate.

Coefficients are stored internally and can be down loaded from a host system or an EPROM. The latter requires no additional support, and PDSP16256 is used in stand alone applications. A full set of coefficients is then automatically loaded at power on, or at the request of the system. A single EPROM can be used to provide coefficients for up to 16 devices.