PDSP16116

`  Complex Number (16+16)*(16+16) Multiplication
`  Full 32-bit Result
`  20MHz Clock Rate
`  Block Floating Point FFT Butterfly Support
`  (-1)*(-1) Trap
`  Two's Complement Fractional Arithmetic
`  TTL Compatible I/O
`  Complex Conjugation
`  2 Cycle Fall Through
`  144-pin PGA or QFP packages

·  Fast Fourier Transforms
·  Digital Filtering
·  Radar and Sonar Processing
·  Instrumentation
·  Image Processing

Supply voltage, V_DD                                 -05V to +7 0V
Input voltage, V_IN                           -0 5V to V_DD +0 5V
Output voltage, V_OUT                      -0 5V to V_DD +0 5V
Clamp diode current per pin, I_K (see note 2)        18mA
Static discharge voltage (HBM)                              500V
Storage temperature, T_S                       -65 to +150
Ambient temperature with power applied, T_AMB
Military grade                                        -55 to +125
Industrial grade                                      -40 to +85
Junction temperature                                            120
Package power dissipation                             1000mW
Thermal resistances
Junction-to-case, _JC                                       12/W
Junction-to-ambient, _JA                                  29/W
NOTES
1. Exceeding these ratings may cause permanent damage.Functional operation under these conditions is not implied.
2. Maximum dissipation should not be exceeded for morethan1 second, only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended periods may affect device reliablity.

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup-port Block Floating Point Arithmetic as used in FFT applications.

The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to output the com-plete complex (32132) bit result within a single cycle. The data format is fractional two's complement.

 In combination with a PDSP16318A, the PDSP16116A forms a two-chip 20MHz complex multiplier accumulator with 20-bit accumulator registers and output shifters. The PDSP16116A in combination with two PDSP16318As and two PDSP1601As forms a complete 20MHz Radix 2 DIT FFT butterfly solution which fully supports block floating point arithmetic. The PDSP16116 has an extremely high throughput that is suited to recursive algorithms as all calculations are performed with a single pipeline delay (two cycle fall-through).