PDSP16112

The PDSP16112 will multiply a complex(16+16) bit data word by a complex(12+12)bit coefficient word and produce a complex (17 +17) bit rounded product.The input data format is two's complement. The device consist of four 16 * 12 multiplier sections based on Booth's "2 bits at a time'algorithm and is plpelined to achieve a 10 MHz throughout. PDSP16112 has many unique featuers: The first one is pipelined architecture. The second one is power dissipation only 500 mW. The third one is TTL compatible inputs. The forth one is advanced 2 micron CMOS process. The fifth one is 20 MHz compex number(16+16)*(12 +12) multiplication.Otherwise, there are also some applications about it.The first one is digital filtering. The second one is fast fourier transforms. The third one is radar and sonar processing. The forth one is instrumentation. The fifth one is automation. The last one is image processing.

There are some absolute maximum ratings about PDSP16112.Supply voltage(Vcc) is -0.5 V to 7.0 V. Input voltage(Vin) is -0.9 V to Vcc+0.9 V. Output voltage(Vout) is -0.9 V to Vcc+0.9 V. Clamp diode current per pin 1K is ±18 mA. Static discharge voltage is 500 V. Storage temperature range(Ts) is -65 to +150.Junction temperature is 150.Ambient temperature with power applied (Tamb) is -40 to +85. Package power dissipation (Ptot) is 1000 mW.(notes: 1.exceeding these ratings cause permanent damage.functional operation under these conditions is not implied.2.maximum dissipation of 1 second should not be exceeded, only one output to be tested at any one time. 3.exposure to absolute maximum ratings for extended periods may affect device reliability.)

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