PDI1394P24

• Fully supports provisions of IEEE 13941995 Standard for high performance serial bus and the P1394a2000 Standard.1
• Fully interoperable with FirewireE and i.LINKE implementations of the IEEE 1394 Standard.2
• Full P1394a support includes:
Connection debounce
Arbitrated short reset
Multispeed concatenation
Arbitration acceleration
Fly-by concatenation
Port disable/suspend/resume
• Provides two 1394a fully-compliant cable ports at 100/200/400 Megabits per second (Mbps)
• Fully compliant with Open HCI requirements
• Cable ports monitor line conditions for active connection to remote node.
• Power down features to conserve energy in battery-powered applications include:
Automatic device power down during suspend
Device power down terminal
Link interface disable via LPS
Inactive ports powered-down
• Logic performs system initialization and arbitration functions
• Encode and decode functions included for data-strobe bit level encoding
• Incoming data resynchronized to local clock
• Single 3.3 volt supply operation
• Minimum VDD of 2.7 V for end-of-wire power-consuming devices
• While unpowered and connected to the bus, will not drive TPBIAS on a connected port, even if receiving incoming bias voltage on that port
• Supports extended bias-handshake time for enhanced interoperability with camcorders
• Interface to link-layer controller supports low-cost bus-holder isolation and optional Annex J electrical isolation
• Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz
• Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
• Does not require external filter capacitors for PLL
• Interoperable with link-layer controllers using 3.3 V and 5 V supplies
• Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies
• Node power class information signaling for system power management
• Cable power presence monitoring
• Separate cable bias (TPBIAS) for each port
• Register bits give software control of contender bit, power class bits, link active bit, and 1394a features
• Function and pin compatible with the Lucent FW802 400 Mbps Phy

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.  These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The PDI1394P24 provides the digital and analog transceiver functions needed to implement a two port node in a cable-based IEEE 13941995 and/or 1394a network. Each cable port incorporates two differential line transceivers.

The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PDI1394P24 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21