PCKEL14

The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal. The PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of -2.375 V to -3.8 V (or 2.375 V to 3.8 V).

The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input.

The common enable (EN) of PCKEL14 is synchronous, so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop PCKEL14 is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

The V_BB pin (an internally generated voltage supply) of PCKEL14 is available to this device only.For single-ended conditions, the unused differential input is connected to V_BB as a switching reference voltage. V_BB of PCKEL14 may also rebias AC-coupled inputs. When used, decouple V_BB and V_CC via a 0.01 F capacitor and limit current sourcing or sinking to 0.1 mA. When not used, V_BB should be left open.