PCK953

Features: • Fully integrated PLL• Output frequency up to 125 MHz in PLL mode• Outputs disable in high impedance• LQFP packaging• 55 ps cycle-to-cycle jitter typical• 9 mA quiescent current, ICCA, typical• 60 ps static phase offset typical• Less than ...

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PCK953 Picture
SeekIC No. : 004456666 Detail

PCK953: Features: • Fully integrated PLL• Output frequency up to 125 MHz in PLL mode• Outputs disable in high impedance• LQFP packaging• 55 ps cycle-to-cycle jitter typicalR...

floor Price/Ceiling Price

Part Number:
PCK953
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

• Fully integrated PLL
• Output frequency up to 125 MHz in PLL mode
• Outputs disable in high impedance
• LQFP packaging
• 55 ps cycle-to-cycle jitter typical
• 9 mA quiescent current, ICCA, typical
• 60 ps static phase offset typical
• Less than 10 mA quiescent current, lCCO, typical



Pinout

  Connection Diagram


Specifications

SYMBOL
PARAMETER
MIN
MAX
UNIT
VCC
Supply voltage
0.3
4.6
V
VI
Input voltage
0.3
VDD+0.3
V
IIN
Input current
±20
mA
Tstg
Storage temperature range
0.3
+125
°C
NOTE:
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.



Description

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.

The PCK953 has a differential LVPECL reference input, along with an external feedback input. These features make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH.

The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 W transmission lines. For series terminated 50 W lines, each of the PCK953 outputs can drive two traces, giving the device an effective fanout of 1:18. The device is packaged in a 7 × 7 mm 32-lead LQFP package to provide the optimum combination of board density and performance.




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