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PCK857

Features: • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications• 1-to-10 differential clock distribution• Very low skew (< 100ps) and jitter (< 100ps)• 3V AVCC and 2.5V Vddq• SSTL_2 interface clock inputs and outputs• CMOS control...

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SeekIC No. : 004456665 Detail

PCK857: Features: • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications• 1-to-10 differential clock distribution• Very low skew (< 100ps) and jitter (< 100p...

PCK857 Data Sheet

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Part Number:
PCK857
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications
• 1-to-10 differential clock distribution
• Very low skew (< 100ps) and jitter (< 100ps)
• 3V AVCC and 2.5V Vddq
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16857 and CBT3857


Pinout

Connection Diagram


Description

Zero delay buffer PCK857 to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable.




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