Features: • PC Card Standard 8.0 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
• PCI Local Bus Specification Revision 2.3 compliant
• PC 98/99 and PC2001 compliant
• Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
• Fully compliant with 1394 Open Host Controller Interface Specification 1.1
• 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports PC Card or CardBus with hot insertion and removal
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
• Supports serialized IRQ with PCI interrupts
• Programmable multifunction terminalsApplication• Card insertion/removal and recognition per the PC Card Standard (release 8.0)
• Speaker and audio applications
• LED socket activity indicatorsSpecificationsSupply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 V to 2.2 V
ANALOGVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
PLLVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Clamping voltage range, VCCP and VCCCB . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input voltage range, VI: PCI, CardBus, PHY, miscellaneous . . .0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI, CardBus, PHY, miscellaneous . .-0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . .±20 mA
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°CDescriptionThe PCI7620 and PCI7420 are four-function PCI devices compliant with PCI Local Bus Specification, Revision 2.3. Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release 8.0). The PCI7420 device provides features that make it the best choice for bridging between the PCI bus, PC Cards, and Smart Cards and supports any combination of 16-bit, CardBus PC Cards, or Smart Card adapter in the socket powered at 5 V or 3.3 V, as required.
There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI7420 device. The PCI7x20 device is register compatible with the Intel 82365SL-DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI7420 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with sustained bursting. The PCI7420 device can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering. Function 2 of the PCI7420 device is an integrated IEEE 1394a-2000 open host controller interface (OHCI) PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI7420 device provides two 1394 ports that have separate cable bias (TPBIAS). The PCI7420 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI7x20 device is compliant with the PCI Bus Power Management Interface Specification. The PCI7420 device supports the D0, D1, D2, and D3 power states.
The PCI7420 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the IEEE 1394 data.
The PCI7420 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The PCI7420 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers.
The PCI7420 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
PCI7420 Data Sheet
