Features: • PC Card Standard 8.0 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
• PCI Local Bus Specification Revision 2.3 compliant
• PC 98/99 and PC2001 compliant
• Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
• 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports PC Card or CardBus with hot insertion and removal
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
• Supports serialized IRQ with PCI interrupts
• Programmable multifunction terminals
• Serial ROM interface for loading subsystem ID and subsystem vendor ID
• ExCA-compatible registers are mapped in memory or I/O space
• Intel 82365SL-DF register compatible
• Supports ring indicate, SUSPEND, and PCI CCLKRUN protocol and PCI bus Lock (LOCK)
• Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
• Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, and ultralow-power sleep mode
• Physical write posting of up to three outstanding transactions
• PCI burst transfers and deep FIFOs to tolerate large host latency
• External cycle timer control for customized synchronization
• Extended resume signaling for compatibility with legacy DV components
• PCI power-management D0, D1, D2, and D3 power states
• Advanced submicron, low-power CMOS technologyApplication• Card insertion/removal and recognition per the PC Card Standard (release 8.0)
• Speaker and audio applications
• LED socket activity indicators
• PC Card controller programming model
• CardBus socket registersSpecificationsSupply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 V to 2.2 V
ANALOGVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
PLLVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Clamping voltage range, VCCP and VCCCB . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input voltage range, VI: PCI, CardBus, PHY, miscellaneous . . .0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI, CardBus, PHY, miscellaneous . .-0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . .±20 mA
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°CDescriptionThe PCI6620 and PCI6420 are three-function PCI devices compliant with PCI Local Bus Specification, Revision 2.3. Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release 8.0). The PCI6x20 device provides features that make it the best choice for bridging between the PCI bus, PC Cards, and Smart Cards and supports any combination of 16-bit, CardBus PC Cards, or Smart Card adapter in the socket powered at 5 V or 3.3 V, as required.
There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI6x20 device. The PCI6x20 device is register compatible with the Intel 82365SL-DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI6x20 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI6x20 device can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering.
The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI6x20 device is compliant with the PCI Bus Power Management Interface Specification. The PCI6x20 device supports the D0, D1, D2, and D3 power states. The PCI6x20 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the data.
The PCI6x20 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The PCI6x20 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers.
Function 3 of the PCI6620 and PCI6420 devices is a dedicated socket that supports SD, MMC, Memory Stick, and Memory Stick-Pro cards. The Flash Media dedicated socket provides separate terminals for SD/MMC and Memory Stick signals so that both an SD/MMC card and a Memory Stick/Memory Stick-Pro card can be used concurrently. Various implementation specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in PCI LOCK, serial and parallel interrupts, PC Card activity indicator LEDs, and other platform specific signals. PCI-compliant general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
The PCI6x20 device is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption.
PCI6420 Data Sheet
