PCI1510R

· A 253-Terminal MicroStar BGA^TM Ball-Grid Array (GVF/ZVF) Package
· 2.5-V Core Logic and 3.3-V I/O with Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments
· Integrated Low-Dropout Voltage Regulator (LDO-VR) Eliminates the Need for an External 2.5-V Power Supply
· Mix-and-Match 5-V/3.3-V 16-Bit PC Cards and 3.3-V CardBus Cards
· A Single PC Card or CardBus Slot with Hot Insertion and Removal
· Parallel Interface to TI TPS2211A Single-Slot PC Card Power Switch
· Burst Transfers to Maximize Data Throughput with CardBus Cards
· Interrupt Configurations: Parallel PCI,Serialized PCI, Parallel ISA, and Serialized ISA
· Serial EEPROM Interface for Loading Subsystem ID, Subsystem Vendor ID, and other Configuration Registers
· Pipelined Architecture for Greater Than 130-Mbps Throughput from CardBus-to-PCI and from PCI-to-CardBus
· Up to Five General-Purpose I/Os
· Programmable Output Select for CLKRUN
· Five PCI Memory Windows and Two I/O Windows Available for the 16-Bit Interface
· Two I/O Windows and Two Memory Windows Available to the CardBus Socket
· Exchangeable-Card-Architecture- (ExCA-) Compatible Registers Are Mapped in Memory and I/O Space
· Intel^TM 82365SL-DF and 82365SL Register Compatible
· Ring Indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
· Socket Activity LED Terminal
· PCI Bus Lock (LOCK)
· Internal Ring Oscillator

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . .−0.5 V to 4.6 V
Clamping voltage range, V_CCP, V_CCCB . . . . . . . . .  −0.5 V to 6 V
Input voltage range, V_I: PCI, miscellaneous . .  −0.5 V to V_CCP + 0.5 V
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_CCCB + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to V_CC + 0.5 V
Output voltage range, VO: PCI, miscellaneous . −0.5 V to V_CCP + 0.5 V
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_CCCB + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) (see Note 1) . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) (see Note 2) . . ±20 mA
Storage temperature range, T_stg . . . . . . . .−65°C to 150°C
Virtual junction temperature, T_J . . . . . . . . . . . . . . . . .  150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V_I > V_CC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V_CCP instead of V_CC. PC Card terminals are measured with respect to V_CCCB. The limit specified applies for a dc condition.
2. Applies for external output and bidirectional buffers. V_O > V_CC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V_CCP instead of V_CC. PC Card terminals are measured with respect to V_CCCB. The limit specified applies for a dc condition.

The controller PCI1510R is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The PCI1510R is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1510R is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1510R internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1510R can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA,and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions of PCI1510R. Many other features designed into the controller, such as a socket activity light-emitting diode (LED) outputs, are discussed in detail throughout this document.

An advanced complementary metal-oxide semiconductor (CMOS) PCI1510R process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.