PCD5095

· 80C51 ports P0, P1, P2 and P3 available for interfacing to display, keyboard, I2C-bus, interrupt sources and/or external memory. Integrated 64 kbyte ROM, 3 kbytes of data memory and 1kbyte System Data RAM. External program memory is addressable up to 128 kbytes
· +2.7 to 5 V port (P0 to P3) interface
· TDMA frame (de)multiplexing, transmission or reception can be programmed for any slot
· Ciphering, scrambling, CRC checking/generation and protected B-fields
· Speech and data buffering space for six handsets
· Local call and B-field loop-back
· Two interrupt lines for BML and DSP to interrupt 80C51
· On-chip, three channel time-multiplexed 8-bit Analog-to-Digital Converter (ADC) for RSSI measurement, one for battery voltage measurement and one channel available for other purposes
· On-chip 8-bit Digital-to-Analog Converter (DAC) for electronic potentiometer function
· Phase error measurement and phase error correction by hardware
· DACs and ADCs for dynamic earpiece and dynamic or electret microphone
· On-chip reference voltage
· On-chip supply for electret microphone
· Very low ohmic buzzer output
· Serial interface to external ADPCM CODEC (PCD5032) or 8 kHz u-law samples
· Speech switch for Digital Telephone Answering Machine (DTAM) connected to SPI interface
· IOMâ-2 interface (Siemens registered trademark)
· Serial interface to synthesizer for frequency programming
· Programmable polarity and timing of radio-control signals
· GMSK pulse shaper
· On-chip comparator for use as data-slicer
· Easy interfacing with radio circuits, operating at other supply voltage (RF supply pin with level shifter for RF signals)
· Low-power oscillator with integrated frequency adjustment
· QFP100 package
· Power-on-reset
· Programmable power-down modes
· Low supply voltage (2.7 to 3.6 V)
· CMOS technology.

The PCD5095 is designed for GAP-compliant business systems, PABX and WLL. Two modes of PCD5095 can be selected: three channel ADPCM CODEC with conversion of ADPCM samples to linear PCM format and vice versa, the second mode copies four ADPCM samples into two IOM data buffers and vice versa.

In both modes the DSP controls the bidirectional data flow from the radio interface and the IOMâ-2 interface. The 80C51 controls the DECT protocol and the IOMâ-2 interface. The performance of the embedded 80C51 microcontroller is twice the performance of the classic architecture. The PCD5095 has 64 kbytes of PROM program memory and 3 kbytes of data memory on-chip. In addition there is 1 kbyte of on-chip data memory that is shared with the Burst Mode Logic (BML), the DSP and the System Data RAM (SDR).