PCD5094

· 80C51 ports P0, P1, P2 and P3 available for interfacing o display, keyboard, I2C-bus, interrupt sources and/or xternal memory. External program memory is ddressable up to 128 kbytes
· +2.7 to 5 V port (P0 to P3) interface
· TDMA frame (de)multiplexing. Transmission or eception can be programmed for any slot
· Ciphering, scrambling, CRC checking/generation and rotected B-fields
· Speech and data buffering space for six handsets
· Local call and B-field loop-back
· Two interrupt lines for BML and DSP to interrupt 80C51
· On-chip, three-channel time-multiplexed 8-bit nalog-to-Digital Converter (ADC) for RSSI easurement, one for battery voltage measurement nd one channel available for other purposes
· On-chip 8-bit Digital-to-Analog Converter (DAC) for lectronic potentiometer function
· Phase error measurement and phase error correction by ardware
· DACs and ADCs for dynamic earpiece and dynamic or lectret microphone
· On-chip reference voltage
· On-chip supply for electret microphone
· Very low ohmic buzzer output
· Serial interface to external ADPCM CODEC (PCD5032) r 8 kHz u-law samples
· Speech switch for Digital Telephone Answering achine (DTAM) connected to SPI interface
· IOM-2 interface (Siemens registered trademark)
· Serial interface to synthesizer for frequency rogramming
· Programmable polarity and timing of radio-control ignals
· GMSK pulse shaper
· On-chip comparator for use as data-slicer
· Easy interfacing with radio circuits, operating at other upply voltage (RF supply pin with level shifter for RF ignals)
· QFP100 package
· Power-on-reset
· Low power oscillator with integrated frequency djustment
· Low supply voltage (2.7 to 3.6 V)
· CMOS technology.

The PCD5094 is designed for GAP-compliant asestations offering conference call between the a/b line nd two handsets and answering machine switch. PCD5094 has an mbedded 80C51 microcontroller with twice the erformance of the classic architecture, 64 kbytes of ROM program memory and 3 kbytes of data memory on hip. In addition there is 1 kbyte of on-chip data memory hat is shared with on-chip Burst Mode Logic (BML) and SP, the System Data RAM (SDR).