PC16550D

Features: ` Capable of running all existing 16450 software.` Pin for pin compatible with the existing 16450 except for CSOUT (24) and NC (29). The former CSOUT and NC pins are TXRDY and RXRDY, respectively.` After reset, all registers are identical to the 16450 register set.` In the FIFO mode tran...

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SeekIC No. : 004455840 Detail

PC16550D: Features: ` Capable of running all existing 16450 software.` Pin for pin compatible with the existing 16450 except for CSOUT (24) and NC (29). The former CSOUT and NC pins are TXRDY and RXRDY, respe...

floor Price/Ceiling Price

Part Number:
PC16550D
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

` Capable of running all existing 16450 software.
` Pin for pin compatible with the existing 16450 except for CSOUT (24) and NC (29). The former CSOUT and NC pins are TXRDY and RXRDY, respectively.
` After reset, all registers are identical to the 16450 register set.
` In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO's to reduce the number of interrrupts presented to the CPU.
` Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data.
` Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data.
` Independently controlled transmit, receive, line status, and data set interrupts.
` Programmable baud generator divides any input clock by 1 to (216 b 1) and generates the 16 c clock.
` Independent receiver clock input.
` MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD).
` Fully programmable serial-interface characteristics:
5-, 6-, 7-, or 8-bit characters
Even, odd, or no-parity bit generation and detection
1-, 1(/2-, or 2-stop bit generation
Baud generation (DC to 1.5M baud).
` False start bit detection.
` Complete status reporting capabilities.
` TRI-STATE. TTL drive for the data and control buses.
` Line break generation and detection.
` Internal diagnostic capabilities:
Loopback controls for communications link fault isolation
Break, parity, overrun, framing error simulation.
` Full prioritized interrupt system controls.





Specifications

Temperature Under Bias. . . . . . . . . . . 0 to +70
Storage Temperature. . . . . . . . . . . -65 to +150
All Input or Output Voltages
with Respect to VSS. . . . . . . . . . . ..-0.5V to +7.0V
Power Dissipation. . . . . . . . . . . .. . . . . . . . . . .1W
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics.



UARTs 1
Max Speed (MBaud) 1.5
FIFO Buffer 16 Bytes
Temperature Min 0 deg C
Temperature Max 70 deg C
Supply Min 4.5 Volt
Supply Max 5.5 Volt
Special Features 16450 Compatible
View Using Catalog





Description

The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART).

Functionally identical to the 16450 on powerup (CHARACTER mode)* the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead.

In PC16550D internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers.

The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters of PC16550D received from the CPU. The CPU PC16550D can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt).

The UART PC16550D includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216b1), and producing a 16 c clock for driving the internal transmitter logic. Provisions are also included to use this 16 c clock to drive the receiver logic. The UART PC16550D has complete MODEM-control capability, and a processor- interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.

The UART PC16550D is fabricated using National Semiconductor's advanced M2CMOS process.






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