Features: • 2.7 to 5.0 V single supply operation• 35 dBm output power at 3.5 V• 55 % Power Added Efficiency• Input matched to 50 • Complete on chip input and interstage matching• Analog power control• Less than 10 mA current consumption in power down mode&...
PBL40310: Features: • 2.7 to 5.0 V single supply operation• 35 dBm output power at 3.5 V• 55 % Power Added Efficiency• Input matched to 50 • Complete on chip input and interstage...
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Parameter |
Conditions |
Symbol |
Min. |
Typ. |
Max. |
Unit |
Supply voltage, continuous |
VCC |
-0.5 |
6.0 |
V | ||
Power control voltage |
VAPC |
-0.5 |
6.0 |
V | ||
Input power |
PIN |
+20 |
dBm | |||
Operating Case Temperature |
TOP |
-40 |
+85 |
|||
Storage Temperature Range |
TSTORAGE |
-30 |
+100 |
The PBL 40310 is a highly integrated single-ended silicon MMIC power amplifier intended for use in GSM terminals. It delivers 35 dBm at 900 MHz with 55 % power added efficiency into a 50 unbalanced load using a single 3.5 V supply.
The circuit PBL40310 has an analog ramp signal to control output power level and a logical on/ off signal for power down mode. PBL40310 can be used in dual-band amplifiers using the band select logical signal. It can be operated up to 50 % duty cycle with minimum performance degradation. The circuit PBL40310 is housed in a specially designed QSOP16 (150 mil body) package and the implementation requires only few external components.
25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process with additional features for improved wireless performance has been used. On-chip capacitors PBL40310 and inductors are used for the integrated internal matching network. Special front-side of PBL40310 metallized substrate contacts provide excellent ground paths from active devices to the highly doped semiconductor substrate and package ground.