PBGA388

At the heart of the STPC Consumer PBGA388 is an advanced processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus) and EIDE controller. The STPC Consumer has in addition to the 5ST86, a Video subsystem and high quality digital Television output.

The STMicroelectronics x86 processor core PBGA388 is embedded with standard and application specific peripheral modules on the same silicon die. The PBGA388 has all the functionality of the STMicroelectronics standard x86 processor products, including the low power System Management Mode (SMM). System Management Mode (SMM) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. While running in isolated SMM address space, the SMM interrupt routine of PBGA388 can execute without interfering with the operating system or application programs. Further power management facilities include a suspend mode that can be initiated from either hardware or software. Because of the static nature of the core, no internal data is lost.

The STPC Consumer PBGA388 makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. PBGA388 significantly reduces total system memory with system performances equal to that of a comparable solution with separate frame buffer and system memory. In addition, memory bandwidth of PBGA388 is improved by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus.

The 64-bit wide memory array of PBGA388 provides the system with 320MB/s peak bandwidth, double that of an equivalent system using 32 bits. This allows for higher screen resolutions and greater color depth. The processor bus of PBGA388 runs at the speed of the processor (DX devices) or half the speed (DX2 devices). The 'standard' PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated with the x86 processor core.

The PCI bus is the main data communication link to the STPC Consumer chip. The STPC Consumer translates appropriate host bus I/O and Memory cycles onto the PCI bus. PBGA388 also supports the generation of Configuration cycles on the PCI bus.

The STPC Consumer, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. PBGA388 contains a PCI arbitration function for three external PCI devices.

The STPC Consumer integrates an ISA bus controller. Peripheral modules such as parallel and serial communications ports, keyboard controllers and additional ISA devices can be accessed by the STPC Consumer chip set through PBGA388 bus. An industry standard EIDE (ATA 2) controller is built in to the STPC Consumer and connected internally via the PCI bus. Graphics functions of PBGA388 are controlled by the on-chip SVGA controller and the monitor display is managed by the 2D graphics display engine.

This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system ith a low silicon area cost. PBGA388 performs limited raphics drawing operations, which include hardware cceleration of text, bitblts, transparent blts nd fills. These operations can act on off-screen r on-screen areas. The frame buffer size of PBGA388 ranges p to 4 Mbytes anywhere in the physical main emory.

The graphics resolution of PBGA388 supported is a maximum f 1280x1024 in 65536 colours at 75Hz refresh ate and PBGA388 is VGA and SVGA compatible. Horizontal iming fields are VGA compatible while the vertical ields are extended by one bit to accommodate the bove display resolution. TPC Consumer provides several additional functions o handle MPEG or similar video streams.

The Video Input Port accepts an encoded digital ideo stream in one of a number of industry standard ormats, decodes PBGA388, optionally decimates PBGA388 by factor of 2:1, and deposits it into an off screen rea of the frame buffer. An interrupt request can e generated when an entire field or frame has een captured.