DescriptionThe PALLV16V8 PALLV16V8Z-20 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology. PALLV16V8Z-20 is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALLV16V8 will directly repl...
PALLV16V8Z-20: DescriptionThe PALLV16V8 PALLV16V8Z-20 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology. PALLV16V8Z-20 is functionally compatible with all 20-pin G...
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DescriptionThe PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electricall...
SpecificationsStorage Temperature . . . . . . . . . . . . . .-65°C to +150°CAmbient Temperature wi...
SpecificationsStorage Temperature . . . . . . . . . . . . . .-65°C to +150°CAmbient Temperature wi...
The PALLV16V8 PALLV16V8Z-20 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology. PALLV16V8Z-20 is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30- µ A maximum standby current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic of PALLV16V8Z-20 can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically.
The fixed OR array of PALLV16V8Z-20 allows up to eight data product terms per output for logic functions. The sum of PALLV16V8Z-20 feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.