PALCE20V8H-10JC

The PALCE20V8H-10JC is a CMOS Flash Erasable second- generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell.

The features of the PALCE20V8H-10JC are: (1)Active pull-up on data input pins; (2)Low power version (20V8L); (3)Standard version has low power; (4)CMOS Flash technology for electrical erasability and reprogrammability; (5)User-programmable macrocell; (6)QSOP package available; (7)High reliability.

The absolute maximum ratings of the PALCE20V8H-10JC are: (1)Storage Temperature: -65 to +150; (2)Ambient Temperature with Power Applied: -55 to +125; (3)Supply Voltage to Ground Potential: -0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High Z State: -0.5V to +7.0V; (5)DC Input Voltage: -0.5V to +7.0V; (6)Output Current into Outputs (LOW): 24 mA; (7)DC Programming Voltage:12.5V; (8)Latch-Up Current: >200 mA.