Features: ` Pin and function compatible with all 20-pin PAL® devices` Electrically erasable CMOS technology provides reconfigurable logic and full testability` High-speed CMOS technology - 5-ns propagation delay for -5 version - 7.5-ns propagation delay for -7 version` Direct plug-in repla...
PALCE16V8H-15PC_4: Features: ` Pin and function compatible with all 20-pin PAL® devices` Electrically erasable CMOS technology provides reconfigurable logic and full testability` High-speed CMOS technology - 5-ns ...
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Storage Temperature | 65 to +150 |
Ambient Temperaturewith Power Applied | 55 to +125 |
Supply Voltage withRespect to Ground | 0.5 V to +7.0 V |
DC Input Voltage | 0.5 V to VCC + 0.5 V |
DC Output or I/OPin Voltage | 0.5 V to VCC + 0.5 V |
Static Discharge Voltage | 2001 V |
Latchup Current(TA = -400 to 85) | 100 mA |
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. PALCE16V8H-15PC_4 is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-A maximum standby current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations of PALCE16V8H-15PC_4 are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically.
The fixed OR array of PALCE16V8H-15PC_4 allows up to eight data product terms per output for logic functions. The sum of PALCE16V8H-15PC_4 feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.