Features: ` Pin and function compatible with all 20-pin GAL devices` Electrically erasable CMOS technology provides reconfigurable logic and full testability` High-speed CMOS technology- 5-ns propagation delay for -5 version- 7.5-ns propagation delay for -7 version` Direct plug-in replacement ...
PALCE16V8: Features: ` Pin and function compatible with all 20-pin GAL devices` Electrically erasable CMOS technology provides reconfigurable logic and full testability` High-speed CMOS technology- 5-ns propag...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Storage Temperature | 65 to +150 |
Ambient Temperaturewith Power Applied | 55 to +125 |
Supply Voltage withRespect to Ground | 0.5 V to +7.0 V |
DC Input Voltage | 0.5 V to VCC + 0.5 V |
DC Output or I/OPin Voltage |
0.5 V to VCC + 0.5 V |
Static Discharge Voltage | 2001 V |
Latchup Current(TA = 0 to 75) | 100 mA |
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. PALCE16V8 is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations of PALCE16V8 are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically.
The fixed OR array ofPALCE16V8 allows up to eight data product terms per output for logic functions. The sum of PALCE16V8 feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
AMD's FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools of PALCE16V8 are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program of PALCE16V8 also greatly reduces design time since a designer can use a tool that is already installed and familiar.