Features: • Single chip IEEE 1284 parallel port termination • 28-pin QSOP package, smallest physical solution• 17 terminating lines in a single package• In-system ESD protection to ±8KV, HBM• In-system ESD protection to ±4KV per IEC 61000-4-2• Protects downstrea...
PACS1284: Features: • Single chip IEEE 1284 parallel port termination • 28-pin QSOP package, smallest physical solution• 17 terminating lines in a single package• In-system ESD protect...
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Features: ·Single chip IEEE 1284 parallel port termination·28 pin QSOP package, smallest physical ...
PARAMETER |
RATING |
UNITS |
VCC Voltage |
6.0 |
V |
Input Voltage Range, no clamping |
-6.0to6.0 |
V |
Storage Temperature Range |
-65 to +150 |
|
Power Dissipation per Resistor |
100 |
mW |
Package Power Dissipation |
1.00 |
W |
California Micro Devices' PACS1284 Parallel Port Termination Network provides a complete integrated solution for the entire IEEE 1284 interface in a single QSOP package.
To support the bi-directional transfer data rates of enhanced high-speed parallel ports, the IEEE 1284 Standard recommends a combined termination/pull-up filter network between the driver/receiver PACS1284 and the cable at both ends of the parallel port interface. In addition, government EMC compatibility requirements impose strict filtering requirements on the parallel port. The California Micro Devices PACS1284 addresses all these requirements by providing a seventeen-line IEEE 1284-compliant network in a thin film integrated circuit. PACS1284 provides a complete parallel port termination solution for space critical applications by integrating a total of 60 discrete components. In addition, all the I/O pins are ESD protected for contact discharges up to ±4KV per the Human Body Model (HBM), with the output pins having the highest probability of ESD pulse exposure protected to ±8KV (HBM), thereby providing the necessary robustness for the port's application environment.
The PACS1284 is manufactured in a 28-pin QSOP package and is available with optional lead-free finishing.