PA7024J-20

The PA7024J-20 is designed as one kind of member of the programmable electrically erasable logic (PEEL) array family based on ICT's CMOS EEPROM technology. PEEL arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today's programmable logic designs.

PA7024J-20 has six features. (1)CMOS electrically erasable technology. (2)Most powerful 24-pin PLD available. (3)Flexible logic cell. (4)High-speed commercial and industrial versions. (5)Ideal for combinatorial, synchronous and asynchronous logic applications. (6)Development and programmer support. Those are all the main features.

Some absolute maximum ratings have been concluded into several points of PA7024J-20 as follow. (1)Its supply voltage would be from -0.5V to 7.0V. (2)Its voltage applied to any pin would be from -0.5V to Vcc+0.6V. (3)Its output current would be +/-25mA. (4)Its storage temperature range would be from -65°C to 150°C. (5)Its lead temperature would be 300°C. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device.

Also some electrical characteristics of PA7024J-20 are concluded as follow. (1)Its output high voltage TTL would be min 2.4V. (2)Its output high voltage CMOS would be min Vcc-0.3V. (3)Its output low voltage TTL would be max 0.5V. (4)Its output low voltage CMOS would be max 0.15V. (5)Its input high level would be min 2.0V and max Vcc+0.3V. (6)Its input low level would be min -0.3V and max 0.8V. (7)Its input leakage current would be max +/-10uA. (8)Its output leakage current would be max +/-10uA. (9)Its output short circuit current would be min -30mA and max -120mA. (10)Its input capacitance would be max 6pF. (11)Its output capacitance would be max 12pF. (12)Its Vcc current would be min 85mA and max 120mA. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!