P89LPC924

Features: ` 4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable page size, and single byte erase.` 256-byte RAM data memory.` Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output.` Real-Time clock that ca...

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SeekIC No. : 004453762 Detail

P89LPC924: Features: ` 4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable page size, and single byte erase.` 256-byte RAM data memory.` Two 16-bit counter/timers. Each timer may be config...

floor Price/Ceiling Price

Part Number:
P89LPC924
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

` 4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable page
  size, and single byte erase.
` 256-byte RAM data memory.
` Two 16-bit counter/timers. Each timer may be configured to toggle a port output
  upon timer overflow or to become a PWM output.
` Real-Time clock that can also be used as a system timer.
` 4-input 8-bit multiplexed A/D converter/single DAC output. Two analog
  comparators with selectable inputs and reference source.
` Enhanced UART with fractional baud rate generator, break detect, framing error
  detection, automatic address detection and versatile interrupt capabilities.
` 400 kHz byte-wide I2C-bus communication port.
` Configurable on-chip oscillator with frequency range and RC oscillator options
  (selected by user programmed Flash configuration bits). The RC oscillator (factory
  calibrated to ±1 %) option allows operation without external oscillator
  components. Oscillator options support frequencies from 20 kHz to the maximum
  operating frequency of 18 MHz. The RC oscillator option is selectable and fine tunable.
` 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).
` 15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset options.
2.2 Additional features
` 20-pin TSSOP package.
` A high performance 80C51 CPU provides instruction cycle times of 111 ns to
  222 ns for all instructions except multiply and divide when executing at 18 MHz.
  This is six times the performance of the standard 80C51 running at the same
  clock frequency. A lower clock frequency for the same performance results in
  power savings and reduced EMI.
` In-Application Programming of the Flash code memory. This allows changing the
  code in a running application.
` Serial Flash programming allows simple in-circuit production coding. Flash
  security bits prevent reading of sensitive application programs.
` Watchdog timer with separate on-chip oscillator, requiring no external
  components. The watchdog prescaler is selectable from eight values.
` Low voltage reset (Brownout detect) allows a graceful system shutdown when
  power fails. May optionally be configured as an interrupt.
` Idle and two different Power-down reduced power modes. Improved wake-up from
  Power-down mode (a low interrupt input starts execution). Typical Power-down
  current is 1 mA (total Power-down with voltage comparators disabled).
` Active-LOW reset. On-chip power-on reset allows operation without external reset
  components. A reset counter and reset glitch suppression circuitry prevent
  spurious and incomplete resets. A software reset function is also available.
` Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
  allowing it to perform an oscillator fail detect function.
` Programmable port output configuration options:
` quasi-bidirectional,
` open drain,
` input-only.
` Port 'input pattern match' detect. Port 0 may generate an interrupt when the value
  of the pins match or do not match a programmable pattern.
` LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.
` Controlled slew rate port outputs to reduce EMI. Outputs have approximately
  10 ns minimum ramp times.
` Only power and ground connections are required to operate the P89LPC924/925
  when internal reset option is selected.
` Four interrupt priority levels.
` Eight keypad interrupt inputs, plus two additional external interrupt inputs.
` Second data pointer.
` Schmitt trigger port inputs.
` Emulation suppor



Pinout

  Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
Tamb(bias) operating bias ambient temperature   -55 +125 °C
Tstg storage temperature range   -65 +150 °C
Vxtal voltage on XTAL1, XTAL2 pin to VSS     VDD + 0.5 v
Vn voltage on any other pin to VSS   -0.5 5.5 v
IOH(I/O) HIGH-level output current per I/O pin     8 mA
IOL(I/O) LOW-level output current per I/O pin     20 mA
II/O(tot)(max) maximum total I/O current     80 mA
Ptot(pack) total power dissipation per package based on package heat
transfer, not device power
consumption
  1.5 w



Description

The P89LPC924/925 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC924/925 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC924/925 in order to reduce component count, board space, and system cost.




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