P87C591SFB_1180310

1.1 80C51 Related Features of the 8xC591
` Full static 80C51 Central Processing Unit available as OTP, ROM and ROMless
` 16 Kbytes internal Program Memory expandable externally to 64 Kbytes
` 512 bytes on-chip Data RAM expandable externally to 64 Kbytes
` Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture & compare) }
` 10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC option
` Two 8-bit resolution, Pulse Width Modulated outputs
` 32 I/O port pins in the standard 80C51 pinout
` I2C-bus serial I/O port with byte oriented master and slave functions
` On-chip Watchdog Timer T3
` Extended temperature range: -40 to +85°C
` Accelerated (prescaler 1:1) instruction cycle time 375 ns @ 16 MHz
` Operation voltage range: 5 V ± 10%
` Security bits:
ROM version has 2 bits
OTP/EPROM version has 3 bits
` 64 bytes Encryption array
` 4 level priority interrupt, 15 interrupt sources
` Full-duplex enhanced UART with programmable Baudrate Generator
` Power Control Modes:
Clock can be stopped and resumed
Idle Mode
Power-down Mode
` ADC active in Idle Mode
` Second DPTR register
` ALE inhibit for EMI reduction
` Programmable I/O port pins (pseudo bi-directional, push-pull, high impedance, open drain)
` Wake-up from Power-down by external interrupts
` Software reset bit (AUXR1.5)
` Low active reset pin
` Power-on detect reset
` Once mode
1.2 CAN Related Features of the 8xC591
` CAN 2.0B active controller, supporting 11-bit Standard and 29-bit Extended indentifiers
` 1 Mbit/s CAN bus speed with 8 MHz clock achievable
` 64 byte receive FIFO (can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet, CANopen and OSEK)
` 13 byte transmit buffer
` Enhanced PeliCAN core (from the SJA1000 stand-alone CAN2.0B controller)
1.2.1 PELICAN FEATURES
` Four independently configurable Screeners (Acceptance Filters)
` Each Screener has tow 32-bit specifiers:
32-bit Match and
32-bit Mask
` 32-bits of Mask per Screener allows unique Group addressing per Screener
` Higher layer protocols especially supported in Standard CAN format with:
Up to four, 11-bit ID Screeners that also Screen the two (2) Data Bytes
i.e., Data Frames are Screened by the CAN ID and by Data Byte content
` Up to eight, 11-bit ID Screeners half of which also Screen the first Data Byte
` All Screeners are changeable "on the fly"
` Listen Only Mode, Self Test Mode
` Error Code Capture, Arbitration Lost Capture, readable Error Counters

The following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. If one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked.

This example does not include any time-out routines. In the slave modes, time-out routines are not very useful since, in these modes, SIO1 behaves essentially as a passive device. In the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. This time period is defined by the system connected to the I2C bus.

Notes
1. The following applies to the Absolute Maximum Ratings:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any conditions other than those described
in the Chapters 24 and 25 of this specification is not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging
effect of excessive static charge. However, its suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect
to VSS unless otherwise noted.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.

The P8xC591 is a single-chip 8-bit-high-performance microcontroller, with on-chip CAN-controller, derived from the 80C51 microcontroller family.

P8xC591 uses the powerful 80C51 instruction set and includes the successful PeliCAN functionality of the SJA1000 CAN controller from Philips Semiconductors.

The fully static core provides extended power save provisions as the oscillator can be stopped and easily restarted without loss of data. The improved internal clock prescaler of 1:1 achieves a 375 ns instruction cycle time at 16 MHz external clock rate.

Figure 1 shows a Block Diagram of the P8xC591. The microcontroller is manufactured in an advanced CMOS process, and is designed for use in automotive and general industrial applications. In addition to the 80C51 standard features, the P8xC591 provides a number of dedicated hardware functions for these applications. Three versions of the P8xC591 will be offered:
` P80C591 (without ROM)
` P83C591 (with ROM)
` P87C591 (with OTP)

Hereafter these versions will be referred to as P8xC591.

The temperature range of P8xC591 includes (max. fCLK = 16 MHz):
` -40 to +85 °C version, for general applications

The P8xC591 combines the functions of the P87C554
(microcontroller) and the SJA1000 (stand-alone
CAN-controller) with the following enhanced features:
` Enhanced CAN receive interrupt (level sensitive)
` Extended acceptance filter
` Acceptance filter changeable "on the fly".
The main differences between P8xC591 and P87C554 are:
` CAN-controller on chip
` 6-input ADC
` Low active Reset
` 44 leads.