Features: • 80C51 central processing unit
• 48 K * 8 ROM, expandable externally to 64 Kbytes
• ROM Code protection
• 1536 * 8 RAM, expandable externally to 64 Kbytes
• Two standard 16-bit timer/counters
• An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
• A 10-bit ADC with eight multiplexed analog inputs and programmable autoscan
• Two 8-bit resolution, pulse width modulation outputs
• Five 8-bit I/O ports plus one 8-bit input port shared with analoginputs
• I2C-bus serial I/O port with byte oriented master and slave functions
• Full-duplex UART compatible with the standard 80C51
• On-chip watchdog timer
• 15 interrupt sources with 2 priority levels (2 to 6 external sources possible)
• Extended temperature range (40 to +85 °C)
• 4.5 to 5.5 V supply voltage range
• Frequency range for 80C51family standard oscillator: 3.5 MHz to 16 MHz
• PLL oscillator with 32 kHz reference and
softwareselectable system clock frequency
• Seconds Timer
• Software enable/disable of ALE output pulse
• Electromagnetic compatibility improvements
• Wakeup from Powerdown by external or seconds interruptSpecifications
|
PARAMETER |
RATING |
UNIT |
|
Storage temperature range |
65 to +150 |
°C |
|
Voltage on VDD to VSS and SCL, SDA to VSS |
0.5 to +6.5 |
V |
|
Input / output current on any I/O pin |
10 |
mA |
|
Power dissipation (based on package heat transfer limitations, not device power consumption) |
1.0 |
W |
DescriptionThe P80C557E6/P83C557E6 (hereafter generically referred to as P8xC557E6) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The P8xC557E6 has the same instruction set as the 80C51. Three versions of the derivative exist:
• P83C557E6 - 48 Kbytes mask programmable ROM
• P80C557E6 - ROMless version of the P83C557E6
The P8xC557E6 contains a non-volatile 48 Kbytes mask programmable ROM (P83C557E6), a volatile 1536 * 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer, an on-chip oscillator and timing circuits. For systems that require extra capability the P8xC557E6 can be expanded using standard TTL compatible memories and logic.
In addition, the P8xC557E6 has two software selectable modes of power reduction - Idle Mode and power-down mode. The Idle Mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode P8xC557E6 saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
The P8xC557E6 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic as well as bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system clock, 58% of the instructions are executed in 0.75 ms and 40% in 1.5 ms. Multiply and divide instructions require 3 ms.
P80C557E6 Data Sheet
