P5Cx80

Standard family features
· EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB
*Data retention time: 20 years minimum
*Endurance: 500000 cycles typical
· ROM: 200 KB
· RAM: 6144 B
*256 B IRAM + 3.25 KB standard RAM usable for CPU
*2560 B FXRAM usable for FameXE
· Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)
*5-metal-layer 0.14 mm CMOS technology
*Operating in Contact and Contactless mode (dependent on family type option)
*Featuring a 24-bit universal memory space, 24-bit program counter
*Combined universal program and data linear address range up to 16 MB
u Additional instructions to improve:
- Pointer operations
- Performance
- Code density of both C and Java source code
· ISO/IEC 7816 contact interface
· PKI coprocessor FameXE
· Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS,Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
*8192 bits maximum key length for RSA with randomly chosen modulus
*4096 bits maximum key length for calculation within RAM
*32-bit interface
*Boolean operations for acceleration of standard, symmetric cipher algorithms
· High speed Triple-DES coprocessor (64-bit parallel processing DES engine)
*Two or three keys loadable
*DES3 performance < 40 ms
· High speed AES coprocessor (128-bit parallel processing AES engine)
· Memory Management Unit (MMU)
· Low power and low voltage design using NXP Semiconductors handshaking technology
· Multiple source vectorized interrupt system with four priority levels
· Watch exception provides software debugging facility
· Multiple source RESET system
· Two 16-bit timers
· High reliable EEPROM for both data storage and program execution
· Bytewise EEPROM programming and read access
· Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at a time
· Typical EEPROM page erasing time: 1.7 ms
· Typical EEPROM page programming time: 1.0 ms
* Power-saving Idle mode
* Wake-up from Idle mode by RESET or any activated interrupt
* Power-saving Sleep (power-down) mode or Clockstop mode
* Wake-up from Sleep or Clockstop mode by RESET or external interrupt
· Contact configuration and serial interface according to ISO/IEC 7816: GND, VDD,CLK, RST_N, IO1
· ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high speed personalization up to 1 Mbit/s
· External or internally generated configurable CPU clock
· 1 MHz to 10 MHz operating external clock frequency range
* Internal CPU clock up to 30 MHz with synchronous operation
* Internal clocking independent of externally applied frequency
· High speed 16-bit CRC engine according to ITU-T polynomial definition
· Low power Random Number Generator (RNG) in hardware, AIS-31 compliant
· 1.62 V to 5.5 V extended operating voltage range for class C, B and A
· Optional extended Class B operation mode (targeted for battery supplied applications)
· -25 °C to +85 °C ambient temperature
· Broad spectrum of delivery types:
* Wafers
* Modules
Product specific family features
· P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144
* ISO/IEC 7816 contact interface
* Two additional IO ports IO2 and IO3 for full-duplex serial data communication
· P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144
* CIU fully compatible with ISO/IEC 14443 A:
- Fully supports the T = CL protocol according ISO/IEC 14443-4
- Data transfer rates supported: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s
* MIFARE contactless interface according ISO/IEC 14443-2:
- 13.56 MHz operating frequency
- Reliable communication due to 100 % ASK
- High speed efficient frame support
- True anticollision
* MIFARE reader infrastructure compatibility
* Optional MIFARE 1 KB and MIFARE 4 KB emulation
* Two additional IO ports IO2 and IO3 for full-duplex serial data communication Security features
· Enhanced security sensors:
* Low and high clock frequency sensor
* Low and high temperature sensor
* Low and high supply voltage sensor
* Single Fault Injection (SFI) attack detection
* Light sensors (included integrated memory light sensor functionality)
· Electronic fuses for safeguarded mode control
· Active shielding
· Unique ID for each die
· Clock input filter for protection against spikes
· Power-up and power-down reset
· Optional programmable card disable feature
· Memory security (encryption and physical measures) for RAM, EEPROM and ROM
· Memory Management Unit (MMU) including memory protection:
* Secure multi application operating systems via two different operation modes:System mode and User mode
* OS controlled access restriction mechanism to peripherals in User mode
* Memory mapping up to 8-MB code memory
* Memory mapping up to 8-MB (64-kbit) data memory
· Optional disabling of ROM read instructions by code executed in EEPROM
· Optional disabling of any code execution out of RAM
· EEPROM programming:
* No external clock
* Hardware sequencer controlled
* On-chip high voltage generation
* Enhanced error correction mechanism
· 64-B or 128-B EEPROM for customer-defined Security FabKey. Featuring batch, wafer or die-individual security data, included encrypted diversification features on request
· 14 B user write protected security area in EEPROM (byte access, inhibit functionality per byte)
· 32 B write once security area in EEPROM (bit access)
· 32 B user read only area in EEPROM (byte access)
· Customer specific EEPROM initialization available

SmartMX family approach
The new CMOS14 SmartMX P5Cx80 family members feature a modular set of devices with:
• 12 KB to 144 KB EEPROM
• 200 KB user ROM
• 6144 B RAM
• High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC)
• Secured dual/triple-DES coprocessor
• Secured AES coprocessor
• Memory Management Unit (MMU)
• ISO/IEC 7816 contact interface
• Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)
• Optional S2C interface for NFC communication link
• 5-metal-layer 0.14 mm CMOS technology
• EEPROM with typical 500000 cycles endurance and minimum 20 years retention time
• Broad spectrum of delivery types
• Optional certified crypto library modules for RSA, ECC, DES, AES, SHA and PRNG

SmartMX family properties
The long-term approved SmartMX P5Cx80 family features a significantly enhanced secure smart card IC architecture. Extended instructions for Java and C code, linear addressing, high speed at low power and a universal memory management unit are among many other improvements added to the classic 80C51 core architecture. The technology transfer step from 5-metal-layer 0.18 mm to 5-metal-layer 0.14 mm CMOS technology offers now even more advantages in terms of security features, memory resources, crypto coprocessor calculation speed for RSA and ECC as well as availability of secure hardware support for 2/3-key Digital Encryption Standard (DES) and Advanced Encryption Standard (AES) operations.

The availability of contact interface, optional contactless or S2C interface enables the easy implementation of native or open platform and multi-application operating systems in market segments like e.g. banking, E-passport, ID card, Health Card, secure access, Java card, Near Field Communication (NFC) connectable mobile hand sets as well as Trusted Platform Modules (TPM).