ORT82G5

Features:

` High-speed SERDES programmable serial data rates of 622 Mbits/s (SONET only), 1.25 Gbits/s, 2.5 Gbits/s, and 3.125 Gbits/s.
` Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock per quad channels (separate PLL per channel).
` Ability to select full-rate or half-rate operation per Tx or Rx channel by setting the appropriate control registers.
` Transmit preemphasis (programmable) for improved receive data eye opening.
` Receiver energy detector to determine if a link is active.
` 32-bit (SONET or 8b/10b) or 40-bit (raw data) paralle internal bus for data processing in FPGA logic.
` Provides a 10 Gbits/s backplane interface to swit h fabric with protection. Also supports port cards at 622 Mbits/s or 2.5 Gbits/s.

3.125 Gbits/s SERDES compliant with XAUI serial data specification for 10 Gbit Ethernet applications with protection.
` Most XAUI features for 10 Gbit Ethernet are embedded including the required link state machine.
` Compliant to fibre-channel physical layer specification.
` Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed backplane data transfer.
` No knowledge of SONET/SDH needed in generic applications. Simply supply data, a 100 MHz-
156.25 MHz reference clock, and, optionally, a frame pulse.
` High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
` Eight-channel HSI function provides 2.5 Gbits/s serial user data interface per channel for a total chip bandwidth of 20 Gbits/s (full duplex).
` SERDES has low-power CML buffers. Support for 1.5 V/1.8 V I/Os.

Programmable STS-12 or STS-48 framing in SONET mode per channel (in version II). OC-192 framing in quad OC-48 (four channels) also supported.
` Powerdown option of SERDES HSI receiver on a per-channel basis.
` Selectable 8b/10b coder/decoder or SONET scrambler/ descrambler (added for version 2).
` SERDES HSI automatically recovers from loss-ofclock once its reference clock returns to normal operating state.
` In-band management and configuration through transport overhead extraction/insertion in SONET mode (version II).
` Supports transparent mode where the only insertion is A1/A2 framing bytes in SONET mode (version II).
` Built-in boundary scan (IEEE ® 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES interface.
` FIFOs align incoming data across all eight channels (all eight channels, two groups of four channels, or four groups of two channels). Alignment is done using comma characters or /A/ in 8b/10b mode or frame pulse in SONET mode (version II). Optional ability to bypass alignment FIFOs for asynchronous operation between channels. (Each channel includes its own clock and frame pulse or comma detect.)
` Frame alignment across multiple ORT82G5 devices for work/protect switching at STS-768/STM256 and above rates in SONET mode.
` Addition of two 4K X 36 dual-port RAMs with access to the programmable logic.
Intellectual Property Features Programmable logic provides a variety of yet-to-be standardized interface functions, including the following Agere ME IP core functions:
` 10 Gbits/s Ethernet as defined by IEEE 802.3ae:
- XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short reach (typically less than 2") interconnect interface.
- X58+ X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet.
- 64b/66b encoders/decoders for 10 Gbits/s Ethernet.
- XAUI to XGMII translator, including dual XAUI protection.
` POS-PHY4 interface for 10 Gbits/s SONET/SDH and OTN systems and some 10 Gbits/s Ethernet systems to allow easy integration of InfiniBand, fibre-channel, and 10 Gbits/s Ethernet in data over fibre applications.
` Ethernet MAC functions at 10/100 Mbits/s, 1 Gbits/s, and 10 Gbits/s.
` Other functions such as fibre-channel and InfiniBand link layer IP cores are also going to be developed.


Specifications

Parameter	Symbol	Min	Max	Unit
Storage Temperature	Tstg	65	150
Power Supply Voltage with Respect to Ground	VDD33	0.3	4.2	V
	VDDIO	0.3	4.2	V
	VDD15	-	2	V
Input Signal with Respect to Ground	VIN	VSS 0.3	VDDIO + 0.3	V
Signal Applied to High-impedance Output	-	VSS 0.3	VDDIO + 0.3	V
Maximum Package Body Temperature	-	-	220

Description

The SERDES block of ORT82G5 can be reset in one of three different ways as follows: on power up, using the hardware reset,
or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to
approximately 80% of the nominal value of 1.5 V. Following this event, the device will be ready for normal operation
after 3 ms.

A hardware reset of ORT82G5 is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES channels and resets all microprocessor and internal registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the
channel configuration register. The ORT82G5 will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four
channels per quad SERDES can be reset by setting the global reset bit GSWRST. The ORT82G5 will be ready for normal
operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES
internal registers and counters. The microprocessor registers are not affected. It should also be noted that the
embedded block cannot be accessed until after FPGA configuration is complete.