ORT4622

Features:

`v Implemented in an ORCA Series 3 FPGA array.
` Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer.
` No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock, and a frame pulse.
` High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
` HSI function uses Lucent Technologies Microelectronics Group's proven 622 Mbits/s serial interface core.
` Four-channel HSI function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 2.5 Gbits/s (full duplex).
` LVDS I/Os compliant with EIA*-644, support hot insertion.
` 8:1 data multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic.
` On-chip phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T Recommendation G.958 (0.6 UIP-P at 250 kHz).
` Powerdown option of HSI receiver on a perchannel basis.
` Highly efficient implementation with only 3% overhead vs. 25% for 8B10B coding.
` In-Band management and configuration.

` Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
` Built-in boundry scan (IEEE† 1149.1 JTAG).

` FIFOs align incoming data across all four channels for STS-48 (2.5 Gbits/s) operation (in quad STS-12 format).

` 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications.

* EIA is a registered trademark of Electronic Industries Association. †IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.


Application

·The combination of ORT4622 and soft IP cores provides a generic data moving solution for non-SONET applications. There is no requirement for SONET knowledge to the users. All that is needed is to supply the embedded core interface with data, clock, and a 8 kHz frame pulse. The provision registers may also need to be set up, and this can be done through either the FPGA MPI or in a state machine in the FPGA section (VHDL code available from Lucent).

·The 8 kHz frame pulse must be supplied to the SYS_FP signal. For generic applications, the frame pulse can be created in FPGA logic from the 77.76 MHz SYS_CLK using a simple resettable counter (the frame pulse should only be high for one cycle of the SYS_CLK). A VHDL core that automatically provides the 8 kHz frame pulse is available from Lucent. Byte-wide data is then sent to each of the transmit channels as follows: the first 36 bytes transferred will be invalid data (replaced by overhead), where the first byte is sent on the rising edge of SYS_CLK when SYS_FP is high. The next 1044 byte positions can be filled with valid data. This will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 kHz frame pulse will be found. Thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data.

·On the receive side, an 8 kHz pulse must again be supplied to SYS_FP. In this case, however, only the signal DATA_RX*_SPE must be monitored for each channel, where a high value on this signal means valid data.

·Again 87 out 90 bytes received (96.7%) will be valid data.

·In order to provide an easy user interface to transfer arbitrary data streams through the ORT4622, Lucent provides a soft Intellectual Property (IP) core called the protocol independent framer, or PI-Framer. This block transfers user format to the one described above and allows for smoothing/rate transfer of this user data.

·This framer works with a single channel at 622 Mbits/s, two channels at 1.25 Gbits/s, or across four channels at 2.5 Gbits/s.

·Backplane Transceiver Core Detailed Description


Specifications

Parameter	Symbol	Min	Max	Unit
Storage Temperature	Tstg	65	150
I/O Supply Voltage with Respect to Ground	VDD	-	4.2	V
Internal Supply Voltage	VDD2	-	3.2
Input Signal with Respect to Ground CMOS I/O 5 V Tolerant I/O	- -	0.5 0.5	VDD + 0.3 5.8	V V
Signal Applied to High-impedance Output	-	0.5	VDD + 0.3	V
Maximum Package Body Temperature	-	-	220
Junction Temperature	TJ	40	125

Description

Timing and simulation output files of ORT2400 from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPSC's internal configuration RAM.

When using the bit stream generator, the user selects options that affect the functionality of the FPSC. Combined with the front-end tools, ORCA Foundry of ORT2400 produces configuration data that implements the various logic and routing options discussed in this data sheet.

FPSC Design Kit Development of ORT2400 is facilitated by an FPSC design kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, HDL gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. The kit's software of ORT2400 couples with ORCA Foundry, providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page of this document.

FPGA Logic of ORT2400 Overview ORCA Series 3 FPGA logic is a new generation of SRAM-based FPGA logic built on the successful Series 2 FPGA line from Lucent Technologies Microelectronics Group, with enhancements and innovations geared toward today's high-speed designs on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA Series 2 devices, the Series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 3 devices of ORT2400 contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges.

ORCA Series 3 FPGA logic of ORT2400 consists of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features.

An array of PLCs ORT2400 is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PICs ORT2400 provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system- level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM).

PLC Logic Each PFU of ORT2400 within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions.

The PFU ORT2400 is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently.

LUTs of ORT2400  may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset.

The SLIC ORT2400 is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC ORT2400 and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA logic, reducing required routing and allowing for real-world system performance.