ORLI10G

Features:

` Provides a line interface-to-interface with various system standards such as OC-192/STM-64 SONET/ SDH, Quad OC-48/STM-16 10 Gbits/s Ethernet, and 10 Gbits/s OTN (digital wrapper/strong FEC) or 12.5 Gbits/s SuperFEC.
` Embedded PLLs with programmable M/N multiplication/division values provide for flexible data rate conversion between line side and system side.
` Line side provides for 16-bit LVDS data with multiple line frequencies supported up to 850 MHz, depending on system standard.
` Line side interface, including timing and jitter specifications, compliant to OIF 99.102.5 standard.
` Receive side interface can be split into four separate asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic.
` Data and clock rates divided by 4 or 8 for use in FPGA logic.
` Direct interface to Agere's 10 Gbits/s MUX (TTRN0110G) and deMUX (TRCV0110G) or 12.5 Gbits/s MUX (TTRN01126) and deMUX (TRCV01126) for XSBI, SFI-4, or SuperFEC applications.
` LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow high-speed operation.
` Low-power LVDS buffers. Intellectual Property Features Programmable logic provides a variety of yet-to-be standardized interface functions, including the following IP core functions:
` 10 Gbits/s Ethernet as defined by IEEE 802.3ae:
- XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short-reach (typically less than 2 in.) interconnect interface.
- Elastic store buffers for clock domain transfer to/ from the XGMII interface.
- X59 + X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet.
- 64b/66b encoders/decoders for 10 Gbits/s Ethernet.
` POS-PHY4 interface for 10 Gbits/s SONET/SDH and OTN systems and some 10 Gbits/s Ethernet systems.
` Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/ SDH MUX/deMUX functions.
` 66-bit word aligner and 64b/66b receive path decoder, 64b/66b transmit path encoder, and 66b/64b transmit path conversion for Ethernet overhead bits. Programmable Features
` High-performance programmable logic:
- 0.16 m 7-level metal technology.
- Internal performance of >250 MHz.
- 400k usable system gates.
- Meets multiple I/O interface standards.
- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
` Traditional I/O selections:
- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
- Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
- Two slew rates supported (fast and slew limited).
- Fast-capture input latch and input flip-flop (FF)
latch for reduced input setup time and zero hold time.
- Fast open-drain drive capability.
- Capability to register 3-state enable signal.
- Off-chip clock drive capability.
- Two input function generator in output path.
` New programmable high-speed I/O:
- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
- Double-ended: LVDS, bused-LVDS, LVPECL.
Programmable parallel termination (100 ) also supported for these I/Os.
- Customer-defined: ability to substitute arbitrary standard cell I/O to meet fast-moving standards.
` New capability to (de)multiplex I/O signals:
- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate).
- New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). Agere Systems Inc. 5 Data Sheet October 2001 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC ORCA ORLI10G Quad 2.5 Gbits/s Programmable Features (continued)
` Enhanced twin-quad programmable function unit (PFU):
- Eight 16-bit look-up tables (LUTs) per PFU.
- Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations.
- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU.
- 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers.
- Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed.
- Flexible fast access to PFU inputs from routing.
- Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
` Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures.
` Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance.
` SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PAL™-like and-or-invert (AOI) in each programmable logic cell.
` New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as:
- 1-512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
- 1-256 x 36 (dual-port, one read/one write).
- 1-1k x 9 (dual-port, one read/one write).
- 2-512 x 9 (dual-port, one read/one write for each).
- 2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
- Supports joining of RAM blocks.
- Two 16 x 8-bit content addressable memory (CAM) support.
- FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
- Constant multiply (8 x 16 or 16 x 8).
- Dual variable multiply (8 x 8).
` Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device.
` Built-in testability:
- Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only.
- Programming and readback through boundaryscan port compliant to IEEE Draft 1532:D1.7.
- TS_ALL testability function to 3-state all I/O pins.
- New temperature-sensing diode.
` Improved built-in clock management with programmable phase-locked loops (PPLLs) provides optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x possible.
` New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.


Specifications

Parameter	Symbol	Min	Max	Unit
Storage Temperature	Tstg	65	150
Power Supply Voltage with Respect to Ground	VDD33	0.3	4.2	V
	VDDIO	0.3	4.2	V
	VDD33, VDD33_A	0.3	2.0	V
	VDD15	0.3	2.0	V
Input Signal with Respect to Ground	VIN	0.3	VDDIO + 0.3	V
Signal Applied to High-impedance Output	-	0.3	VDDIO + 0.3	V
Maximum Package Body Temperature	-	-	220

Description

The SLIC ORLI10G is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC ORLI10G and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-world system performance.


The Series 4 PIO ORLI10G addresses the demand for the flexibility to select I/Os that meet system interface requirements.

I/Os of ORLI10G can be programmed in the same manner as in previous ORCA devices, with the additional new features that allow the user the flexibility to select new I/O types that support high-speed interfaces.

Each PIO ORLI10G contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/flip-flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. ORLI10G may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU.

On the output side of each PIO ORLI10G, an output from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals.

The output FF of ORLI10G, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered.

The Series 4 I/O logic of ORLI10G has been enhanced to include modes for speed uplink and downlink capabilities.

These modes of ORLI10G are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock.

The new programmable I/O cell of ORLI10G allows designers to select I/Os which meet many new communication standards, permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, singleended, and differential-pair signaling (as shown in Table 1). Based on a programmable, bank-oriented I/O ring architecture, designs of ORLI10G can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels.

The abundant routing resources of the Series 4 architecture of ORLI10G are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance.

Eight fully distributed primary clocks of ORLI10G are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing are available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic.

The improved routing resources of ORLI10G offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.

10 Agere Systems Inc.

Data Sheet 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC October 2001
ORCA ORLI10G Quad 2.5 Gbits/s System-Level Features The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly tuned networking specific phaselocked loops. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems.

Microprocessor Interface The MPI ORLI10G provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16-, and 32-bit interfaces with optional parity to the Motorola ® PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 embedded system bus at 66 MHz performance.

A system-level microprocessor interface of ORLI10G to the FPGA user-defined logic following configuration, through the system bus, including access to the embedded block RAM and general user-logic, is provided by the MPI.

The MPI ORLI10G supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes).

System Bus An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the embedded system bus of ORLI10G offers arbiter, decoder, master, and slave elements.

The system bus control registers of ORLI10G can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or port clock (for JTAG configuration modes).

Phase-Locked Loops of ORLI10G Up to eight PLLs are provided on each Series 4 device, with four PLLs generally provided for FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.

Additional highly tuned and characterized, dedicated phase-locked loops (DPLLs) of ORLI10G are included to ease system designs. These DPLLs meet ITU-T G.811 primaryclocking specifications and enable system designers to very tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are targeted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 systems.

Embedded Block RAM New 512 x 18 quad-port RAM blocks of ORLI10G are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories.

The EBRs of ORLI10G include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus.

Additional logic of ORLI10G has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k, including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at ORLI10G configuration time.