OR3LP26B

Features:

`The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative programmable clock manager (PCM). These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed systems. Since these and all other Series 3 features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.


Specifications

Parameter	Symbol	Min	Max	Unit
Storage Temperature	Tstg	65	150
I/O and ASIC Supply Voltage with Respect to Ground	VDD	-	4.2	V
Internal FPGA Supply Voltage with Respect to Ground	VDD2	-	3.2	V
Input Signal with Respect to Ground CMOS Inputs 5 V Tolerant Inputs	- -	0.5 0.5	VDD + 0.3 5.8	V V
Signal Applied to High-impedance Output	-	0.5	VDD + 0.3

Note: For PCI bus signals used for 5 V signaling and FPGA inputs used as 5 V tolerant, the maximum value is 5.8 V.


Description

The OR3LP26B PIC addresses the demand for everincreasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressCLK. This latch of OR3LP26B is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals of OR3LP26B are available to the PLC array from each PIO, and the ORCA Series 2 capability to use any input pin as a clock or other global input is maintained.

On the output side of each PIO of OR3LP26B , two outputs from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals.

The output FF of OR3LP26B, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is the same as the ORCA Series 3 buffer.

System Features The OR3LP26B also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative programmable clock manager (PCM). These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed systems. Since these and all other OR3LP26B features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.

Routing The abundant routing resources of OR3LP26B FPGA logic are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast ExpressCLK pins.

ExpressCLKs of OR3LP26B may be glitchlessly and independently enabled and disabled with a programmable control signal using the new StopCLK feature. The improved PIC routing resources are now similar to the patented intra- PLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility of OR3LP26B translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.