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OR2T04A-2BA100

Features: High-performance, cost-effective, low-power 0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS technology (OR2TxxA), and 0.25 m CMOS technology(OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade)High density (up to 43,200 usable, logic-only gates; or 99,400 ga...

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OR2T04A-2BA100: Features: High-performance, cost-effective, low-power 0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS technology (OR2TxxA), and 0.25 m CMOS technology(OR2TxxB), (four-input look-up table (LUT) delay le...

OR2T04A-2BA100 Data Sheet

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Part Number:
OR2T04A-2BA100
Supply Ability:
5000

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Product Details

Description



Features:

 High-performance, cost-effective, low-power 0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS technology (OR2TxxA), and 0.25 m CMOS technology(OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade)
 High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM)
 Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis)
 Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures
 Eight 3-state buffers per PFU for on-chip bus structures
 Fast, on-chip user SRAM has features to simplify RAM design and increase RAM speed:
     - Asynchronous single port: 64 bits/PFU
     - Synchronous single port: 64 bits/PFU
     - Synchronous dual port: 32 bits/PFU
 Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers
 Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU):
   - 8 x 8 multiplier requires only 16 PFUs
   - 30% increase in speed
 Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable
 Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry       operation
 Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without    sacrificing performance
 Upward bit stream compatible with the ORCA ATT2Cxx/ ATT2Txx series of devices
 Pinout-compatible with new ORCA Series 3 FPGAs
 TTL or CMOS input levels programmable per pin for the OR2CxxA (5 V) devices
 Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source
 Built-in boundary scan (IEEE*1149.1 JTAG) and 3-state all I/O pins, (TS_ALL) testability functions
 Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP)
 Full PCI bus compliance for all devices
Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ORCA Foundry Development System support (for back-end  implementation)
 New, added features (OR2TxxB) have:
    - More I/O per package than the OR2TxxA family
    - No dedicated 5 V supply (VDD5)
    - Faster configuration speed (40 MHz)
    - Pin selectable I/O clamping diodes provide 5V or 3.3V PCI compliance and 5V tolerance
    - Full PCI bus compliance in both 5V and 3.3V PCI systems 


Specifications

Parameter Symbol Min Max Unit
Storage Temperature Tstg 65 150 °C
Supply Voltage with Respect to Ground VDD 0.5 7.0 V
VDD5 Supply Voltage with Respect to Ground
(OR2TxxA)		 VDD5 VDD 7.0 V
Input Signal with Respect to Ground
OR2TxxA only		 - 0.5 VDD + 0.3
VDD5 + 0.3		 V
Signal Applied to High-impedance Output
OR2TxxA only		 - 0.5 VDD + 0.3
VDD5 + 0.3		 V
Maximum Soldering Temperature - - 260 °C



Description

The OR2T04A-2BA100SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources.

The OR2T04A-2BA100 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each
other. The usable gate counts associated with each series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and temperature ranges.

The FPGA OR2T04A-2BA100 consists of two basic elements: programmable logic cells (PLCs) and programmable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and
configuration RAM. All logic of OR2T04A-2BA100 is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs).

The PLC architecture of OR2T04A-2BA100 provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction.

Some examples of the resources required and the performance that can be achieved using these OR2T04A-2BA100 are represented in Table 2.




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