Features: High-performance, cost-effective, low-power 0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS technology (OR2TxxA), and 0.25 m CMOS technology(OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade)High density (up to 43,200 usable, logic-only gates; or 99,400 ga...
OR2T04A-2BA100: Features: High-performance, cost-effective, low-power 0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS technology (OR2TxxA), and 0.25 m CMOS technology(OR2TxxB), (four-input look-up table (LUT) delay le...
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Parameter | Symbol | Min | Max | Unit |
Storage Temperature | Tstg | 65 | 150 | °C |
Supply Voltage with Respect to Ground | VDD | 0.5 | 7.0 | V |
VDD5 Supply Voltage with Respect to Ground (OR2TxxA) |
VDD5 | VDD | 7.0 | V |
Input Signal with Respect to Ground OR2TxxA only |
- | 0.5 | VDD + 0.3 VDD5 + 0.3 |
V |
Signal Applied to High-impedance Output OR2TxxA only |
- | 0.5 | VDD + 0.3 VDD5 + 0.3 |
V |
Maximum Soldering Temperature | - | - | 260 | °C |
The OR2T04A-2BA100SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources.
The OR2T04A-2BA100 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each
other. The usable gate counts associated with each series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and temperature ranges.
The FPGA OR2T04A-2BA100 consists of two basic elements: programmable logic cells (PLCs) and programmable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and
configuration RAM. All logic of OR2T04A-2BA100 is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs).
The PLC architecture of OR2T04A-2BA100 provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction.
Some examples of the resources required and the performance that can be achieved using these OR2T04A-2BA100 are represented in Table 2.