OCX160

Features:

• 667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth
• Low power CMOS, 2.5V and 3.3V power supply
• SRAM-based, in-system programmable
• 160 configurable I/O ports
80 dedicated differential input ports
80 dedicated differential output ports
Supports LVDS and LVPECL I/O
LVTTL control interface
Output Enable control for all outputs
• Non-blocking switch matrix
Patented ActiveArray™ matrix for superior performance
Double-buffered configuration RAM cells for simultaneous global updates
ImpliedDisconnect™ function for single cycle disconnect/ connect
• Full Broadcast and multicast capability
One-to-One and One-to-Many connections
Special broadcast mode routes one input to all outputs at maximum data rate
• Registered and flow-through data modes
333 MHz synchronous mode
667 Mb/s asynchronous mode
Low jitter and signal skew
Low duty cycle distortion
• RapidConfigure™ parallel interface for configuration and readback
• JTAG serial interface for configuration and Boundary Scan testing
• 420 BGA package with 1.27mm ball spacing


Application

• SONET/SDH and DWDM
• Digital Cross-Connects
• System Backplanes and Interconnects
• High Speed Test Equipment
• ATM Switch Cores
• Video Switching


Specifications

Symbol	Parameter	Limits	Units
VDD.CORE	Supply Voltage (core)	-0.3 to +3.0	V
VDD.IN	Supply Voltage (inputs)	-0.3 to +3.6	V
VDD.PAD	Supply Voltage (differential outputs)	-0.3 to +3.6	V
VIN2	Input Voltage	-0.3 to +3.63	V
TJ	Junction Temperature	+150	°C
TSTG	Storage Temperature	-65 to +150	°C
PMAX	Maximum Power Dissipation	6	W
ESD6	Electrostatic Discharge	2000	V

Description

The OCX160 of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports support flow-through mode only. The output ports are individually programmable to operate in either flowthrough (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global clock or a next neighbor clock source.

The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. The OCX160 support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on all unchanged data paths.

The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to download configuration data to the device and readback data. A functional block diagram of the OCX160 is shown in Figure 1.