NT7181

Features:

 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
 Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
 Operates From a Single 3.3V Supply With 250mW (Typ)
 Low profile 56 Lead TSSOP Package
Clock edge Programmable for Transmitter
Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
Supports Spread Spectrum Clock Generator
Suggests to use for LCD monitor only
No External Components Required for PLL


Pinout




Specifications

Supply voltage range, V_CC (see Note1).................-0.3V to 4V
Output voltage range, V_O.....................-0.3V to V_CC +0.3V
Input voltage range, V_I.......................0.3V to Vcc +0.3V
Storage temperature range, Tstg..................-65°C to 150°C
Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds.....260°C
Junction Temperature................................150°C

# Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.


Description

The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphic controllers. The transmitter can be programmed for rising edge strobe(RFB=1) or falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.

The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (PWDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.