Features: • Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0/BA1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 8192 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
• -7K parts for PC133 2-2-2 operation
-75B parts for PC133 3-3-3 operation
-8B parts for PC100 2-2-2 operationPinout
DescriptionThe NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT(L) are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC's advanced 256Mbit single transistor CMOS DRAM process
technology.
The device NT5SV16M16AT(L) is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output(I/O or DQ) circuits are synchronized with the positiveedge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes of NT5SV16M16AT(L) are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device NT5SV16M16AT(L) by address inputs A0-A12, BA0, BA1 during a mode register setcycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, CAS latency, and speed grade of the device NT5SV16M16AT(L). Auto Refresh (CBR) and Self Refresh operation are supported.
NT5SV16M16AT(L) Data Sheet
