Features: • DDR 512M bit, die B, based on 110nm design rules
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2 / 2.5 (6K & 75B), 2.5 / 3 (5T)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.5V ± 0.2V (6K & 75B)
• VDD = VDDQ = 2.6V ± 0.1V (5T)Specifications
|
Symbol |
Parameter |
Rating |
Units |
|
VIN, VOUT |
Voltage on I/O pins relative to VSS |
−0.5 to VDDQ+ 0.5 |
V |
|
VIN |
Voltage on Inputs relative to VSS |
−0.5 to +3.6 |
V |
|
VDD |
Voltage on VDD supply relative to VSS |
−0.5 to +3.6 |
V |
|
VDDQ |
Voltage on VDDQ supply relative to VSS |
−0.5 to +3.6 |
V |
|
TA |
Operating Temperature (Ambient) |
0 to +70 |
|
|
TSTG |
Storage Temperature (Plastic) |
−55 to +150 |
|
|
PD |
Power Dissipation |
1.0 |
W |
|
IOUT |
Short Circuit Output Current |
50 |
mA |
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.DescriptionNT5DS128M4BF, NT5DS128M4BT, NT5DS64M8BF, NT5DS64M8BT, NT5DS32M16BF and NT5DS32M16BT are die B of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya's 110 nm design process.
The 512Mb DDR SDRAM NT5DS128M4BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM NT5DS128M4BF uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM NT5DS128M4BF during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes.
The 512Mb DDR SDRAM NT5DS128M4BF operates from a differential clock (CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM NT5DS128M4BF are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM NT5DS128M4BF provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs NT5DS128M4BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided by NT5DS128M4BF along with a power-saving Power Down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
NT5DS128M4BF Data Sheet
